C167CS-4RM datasheet(76/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-26

V2.0, 2000-07

Figure 4-7

Several addressing modes use register CP implicitly for address calculations. The

addressing modes mentioned below are described in Chapter 24.

Short 4-Bit GPR Addresses (mnemonic: Rw or Rb) specify an address relative to the

memory location specified by the contents of the CP register, i.e. the base of the current

Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the

short 4-bit GPR address is either multiplied by two or not before it is added to the

content of register CP (see Figure 4-8). Thus, both byte and word GPR accesses are

possible in this way.

GPRs used as indirect address pointers are always accessed wordwise. For some

instructions only the first four GPRs can be used as indirect address pointers. These

GPRs are specified via short 2-bit GPR addresses. The respective physical address

calculation is identical to that for the short 4-bit GPR addresses.

Short 8-Bit Register Addresses (mnemonic: reg or bitoff) within a range from F0H to

FFH interpret the four least significant bits as short 4-bit GPR address, while the four

most significant bits are ignored. The respective physical GPR address calculation is

identical to that for the short 4-bit GPR addresses. For single bit accesses on a GPR, the

GPR’s word address is calculated as just described, but the position of the bit within the

word is specified by a separate additional 4-bit value.

MCD02003

R10

R11

R12

R13

R14

R15

Context

Pointer

(CP) + 30

(CP) + 28

(CP) + 2

(CP)

Internal RAM

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