C167CS-4RM datasheet(75/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-25

V2.0, 2000-07

The Context Pointer CP

This non-bit addressable register is used to select the current register context. This

means that the CP register value determines the address of the first General Purpose

GPRs.

Note: It is the user’s responsibility that the physical GPR address specified via CP

condition is not met, unexpected results may occur.

• Do not set CP below the IRAM start address, i.e. 00’FA00H/00’F600H/00’F200H

(referring to an IRAM size of 1/2/3 KByte)

• Do not set CP above 00’FDFEH

• Be careful using the upper GPRs with CP above 00’FDE0H

The CP register can be updated via any instruction which is capable of modifying an SFR.

Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR

address calculations of the instruction immediately following the instruction

updating the CP register.

The Switch Context instruction (SCXT) allows to save the content of register CP on the

stack and updating it with a new value in just one machine cycle.

Context Pointer

SFR (FE10H/08H)

Reset Value: FC00H

9876

543210

1111

Bit

Function

Modifiable portion of register CP

Specifies the (word) base address of the current register bank.

When writing a value to register CP with bits CP.11 … CP.9 = ‘000’, bits

CP.11 … CP.10 are set to ‘11’ by hardware, in all other cases all bits of

bit field “cp” receive the written value.

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