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C167CS-4RM 数据表(PDF) 72 Page - Infineon Technologies AG |
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C167CS-4RM 数据表(HTML) 72 Page - Infineon Technologies AG |
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72 / 517 page ![]() C167CS Derivatives The Central Processing Unit (CPU) User’s Manual 4-22 V2.0, 2000-07 The Data Page Pointers DPP0, DPP1, DPP2, DPP3 These four non-bit addressable registers select up to four different data pages being active simultaneously at run-time. The lower 10 bits of each DPP register select one of the 1024 possible 16-KByte data pages while the upper 6 bits are reserved for future use. The DPP registers allow to access the entire memory space in pages of 16 KBytes each. DPP0 Data Page Pointer 0 SFR (FE00H/00H) Reset Value: 0000H 15 14 13 12 11 10 9876 543210 -- ---- DPP0PN - - - - - - rw DPP1 Data Page Pointer 1 SFR (FE02H/01H) Reset Value: 0001H 15 14 13 12 11 10 9876 543210 -- ---- DPP1PN - - - - - - rw DPP2 Data Page Pointer 2 SFR (FE04H/02H) Reset Value: 0002H 15 14 13 12 11 10 9876 543210 -- ---- DPP2PN - - - - - - rw DPP3 Data Page Pointer 3 SFR (FE06H/03H) Reset Value: 0003H 15 14 13 12 11 10 9876 543210 -- ---- DPP3PN - - - - - - rw |
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