C167CS-4RM datasheet(91/517 Pages) INFINEON

91 / 517 page

C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-8

V2.0, 2000-07

Interrupt Priority Level and Group Level

The four bits of bit field ILVL specify the priority level of a service request for the

arbitration of simultaneous requests. The priority increases with the numerical value of

ILVL, so 0000B is the lowest and 1111B is the highest priority level.

When more than one interrupt request on a specific level gets active at the same time,

the values in the respective bit fields GLVL are used for second level arbitration to select

one request for being serviced. Again the group priority increases with the numerical

value of GLVL, so 00B is the lowest and 11B is the highest group priority.

Note: All interrupt request sources that are enabled and programmed to the same

priority level must always be programmed to different group priorities. Otherwise

an incorrect interrupt vector will be generated.

Upon entry into the interrupt service routine, the priority level of the source that won the

arbitration and who’s priority level is higher than the current CPU level, is copied into bit

field ILVL of register PSW after pushing the old PSW contents on the stack.

The interrupt system of the C167CS allows nesting of up to 15 interrupt service routines

of different priority levels (level 0 cannot be arbitrated).

Interrupt requests that are programmed to priority levels 15 or 14 (i.e. ILVL = 111XB) will

be serviced by the PEC, unless the COUNT field of the associated PECC register

contains zero. In this case the request will instead be serviced by normal interrupt

processing. Interrupt requests that are programmed to priority levels 13 through 1 will

always be serviced by normal interrupt processing.

Note: Priority level 0000B is the default level of the CPU. Therefore a request on level 0

will never be serviced, because it can never interrupt the CPU. However, an

enabled interrupt request on level 0000B will terminate the C167CS’s Idle mode

and reactivate the CPU.

For interrupt requests which are to be serviced by the PEC, the associated PEC channel

number is derived from the respective ILVL (LSB) and GLVL (see Figure 5-1). So

programming a source to priority level 15 (ILVL = 1111B) selects the PEC channel group

7 … 4, programming a source to priority level 14 (ILVL = 1110B) selects the PEC channel

group 3 … 0. The actual PEC channel number is then determined by the group priority

field GLVL.

Simultaneous requests for PEC channels are prioritized according to the PEC channel

number, where channel 0 has lowest and channel 8 has highest priority.

Note: All sources that request PEC service must be programmed to different PEC

channels. Otherwise an incorrect PEC channel may be activated.

C167CS-4RM 数据表(PDF) 91 Page - Infineon Technologies AG

C167CS-4RM 数据表(HTML) 91 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载