C167CS-4RM datasheet(18/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-1

V2.0, 2000-07

Architectural Overview

The architecture of the C167CS combines the advantages of both RISC and CISC

processors in a very well-balanced way. The sum of the features which are combined

result in a high performance microcontroller, which is the right choice not only for today’s

applications, but also for future engineering challenges. The C167CS not only integrates

a powerful CPU core and a set of peripheral units into one chip, but also connects the

units in a very efficient way. One of the four buses used concurrently on the C167CS is

the XBUS, an internal representation of the external bus interface. This bus provides a

standardized method of integrating application-specific peripherals to produce

derivatives of the standard C167CS.

Figure 2-1

C167CS Functional Block Diagram

C166-Core

CPU

Interrupt Bus

XTAL

MCB04323_7CSR

Osc / PLL

RTC

WDT

Interrupt Controller 16-Level

Priority

PEC

External Instr. / Data

GPT

SSC

BRGen

(SPI)

ASC0

BRGen

(USART)

ADC

10-Bit

16+8

Channels

PWM

CCOM1

CCOM2

EBC

XBUS Control

External Bus

Control

IRAM

Internal

RAM

3 KByte

ProgMem

ROM

32 KByte

Data

CAN1

Rev 2.0B active

Instr. / Data

Port 0

XRAM

6+2 KByte

Port 1

Port 5

Port 3

Port 7

Port 8

Peripheral Data Bus

CAN2

Rev 2.0B active

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