C167CS-4RM datasheet(94/517 Pages) INFINEON

94 / 517 page

C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-11

V2.0, 2000-07

CPU priority ILVL defines the current level for the operation of the CPU. This bit field

reflects the priority level of the routine that is currently executed. Upon the entry into an

interrupt service routine this bit field is updated with the priority level of the request that

is being serviced. The PSW is saved on the system stack before. The CPU level

determines the minimum interrupt priority level that will be serviced. Any request on the

same or a lower level will not be acknowledged.

The current CPU priority level may be adjusted via software to control which interrupt

request sources will be acknowledged.

PEC transfers do not really interrupt the CPU, but rather “steal” a single cycle, so PEC

services do not influence the ILVL field in the PSW.

Hardware traps switch the CPU level to maximum priority (i.e. 15) so no interrupt or PEC

requests will be acknowledged while an exception trap service routine is executed.

Note: The TRAP instruction does not change the CPU level, so software invoked trap

service routines may be interrupted by higher requests.

Interrupt Enable bit IEN globally enables or disables PEC operation and the

acceptance of interrupts by the CPU. When IEN is cleared, no new interrupt requests

are accepted by the CPU. Requests that already have entered the pipeline at that time

will process, however. When IEN is set to ‘1’, all interrupt sources, which have been

individually enabled by the interrupt enable bits in their associated control registers, are

globally enabled.

Note: Traps are non-maskable and are therefore not affected by the IEN bit.

C167CS-4RM 数据表(PDF) 94 Page - Infineon Technologies AG