STLC60135 datasheet(1/25 Pages) STMICROELECTRONICS

部件名	STLC60135

功能描述	TOSCA ADSL DMT TRANSCEIVER

PDF	25 Pages

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制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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1 / 25 page

DTM modem for ADSL, compatible with the

following standards:

– ANSI T1.413 Issue 2

– ITU-T G.992.1 (G.dmt)

– ITU-T G.992.2 (G.lite)

Same chip for both ATU-C and ATU-R

Supports either ATM (Utopia level 1 & 2) or bit-

stream interface

16 bit multiplexed microprocessor interface (lit-

tle and big endian compatibility)

Analog Front End management

Dual latency paths: fast and interleaved

ATM’s PHY layer: cell processing (cell deline-

ation, cell insertion, HEC)

ADSL’s overhead management

Reed Solomon encode/decode

Trellis encode/decode (Viterbi)

DMT mapping/ demapping over 256 carriers

Fine (2ppm) timing recover using Rotor and

Adaptative Frequency Domain Equalizing

Time Domain Equalization

Front end digital filters

0.35

µm HCMOS6 Technology

144 pin PQFP package

Power Consumption 1 Watt at 3.3V

Applications

ATU-C: DSLAM, Routers at Central Office

ATU-R: Routers at SOHO, stand-alone mo-

dems, PC mother boards

General Description

The STLC60135 is the DMT modem and ATM

framer of the STMicroelectronics Tosca

™ chipset.

When coupled with STLC60134 analog front-end

and an external controller running dedicated firm-

ware, the product fulfils ANSI T1.413 “Issue 2”

DMT ADSL specification.

The STLC60135 may be used at both ends of

ADSL loop: ATU-C and ATU-R. The chip sup-

ports UTOPIA level 1 and UTOPIA level 2 inter-

face and a non ATM synchronous bit-stream in-

terface.

September 1999

®

PQFP144

ORDERING NUMBER: STLC60135

STLC60135

TOSCA

™ ADSL DMT TRANSCEIVER

TEST

MODULE

DATA SYMBOL TIMING UNIT

VCXO

DSP

FRONT-END

FFT/IFFT

ROTOR

TRELLIS

CODING

MAPPER/

DEMAPPER

GENERIC

TC

REED/

SOLOMON

ATM

SPECIFIC

TC

INTERFACE

MODULE

CONTROLLER INTERFACE

AFE

CONTROL

INTERFACE

TEST SIGNALS

CLOCK

STM

UTOPIA

AFE

INTERFACE

D98TL315

AFE

CONTROL

CONTROLLER BUS

GENERAL PURPOSE I/Os

Figure 1. Block Diagram

1/25

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