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STLC60135 数据表(PDF) 19 Page - STMicroelectronics

部件名 STLC60135
功能描述  TOSCA ADSL DMT TRANSCEIVER
PDF  25 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLC60135 数据表(HTML) 19 Page - STMicroelectronics

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0123
8
minimum 8 cycles
STM_CLOCK
UNDEFINED
UNDEFINED
FRAME
VALID
b7
b5
b3
b1
b6
b4
b2
b0
one byte as 4 times 2 bits
SLR_DATA(1)
SLR_DATA(0)
SLR_VAL must not repeat in
a 8 clock cycle period
D98TL334
Figure 23. ReceiveSLAP Interface Timing
The implementation must guarantee that all ac-
tive SLR_Valid signals must be separated by at
least 8 clock cycles.
Refer to Figure 23. The SLR_FRAME signals are
asserted when the first pair of bits of a frame are
transferred. For the fast channel a frame is de-
fined as a superframe timebase.
For the interleaved channel the frame is defined
by a timebase
period of 4 superframes. Both
timebases are synchronized to the data flow.
Transmit SLAP Interface
The Transmit interface uses the following signals
(refer to Figure 24)
- SLT_REQ: byte request
- SLT_FRAME: start of frame indication
- SLT_DATA [1:0] data pins, a byte is transferred
2 bits at the time in 4 successive clock cycles.
MSB first, odd bits on SLT_DATA [1]
The logical timing diagram is shown in Figure 25.
The delay between Request and the associated
data byte is defined as 8 cycles.
The SLT_FRAME signals are asserted when the
first pair of bits of a frame are transferred. For the
fast channel a frame is defined as a superframe
timebase.
For the interleaved channel the frame is defined
by a timebase period of 4 superframes.
Both timebases are synchronized to the data flow
and guarantee that the frame indication is as-
serted when the first bits of the first DMT symbol
are transferred.
08
9
1
CLOCK
UNDEFINED
SLT_FRAME
SLT_REQUEST
b7
b5
b3
b1
b6
b4
b2
b0
one byte in 4 cycles
SLT_DATA(1)
SLT_DATA(0)
repeated each superframe/
S-frame
D98TL336
11
1
02
STM_CLOCK
Request may be repeated after 4 cycles
Delay Request-Data equals 8 cycles
UNDEFINED
Figure 25. Transmit SLAP Interface Timing
Diagram
EXTERNAL
COMPONENT
(SLAVE)
MODEM
(MASTER)
D98TL335
CLOCK
DATA
2
REQUEST
FRAME
Figure 24. Interface Towards PHY Layer
Tper
Th
Ti
CLOCK
ALL INPUTS
ALL OUTPUTS
Ts
Thd
Td
D98TL337
Figure 26. InterfaceTiming
STLC60135
19/25



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