| 数据搜索系统,热门电子元器件搜索 |
|
STLC60135 数据表(PDF) 19 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLC60135 数据表(HTML) 19 Page - STMicroelectronics |
|
19 / 25 page ![]() 0123 8 minimum 8 cycles STM_CLOCK UNDEFINED UNDEFINED FRAME VALID b7 b5 b3 b1 b6 b4 b2 b0 one byte as 4 times 2 bits SLR_DATA(1) SLR_DATA(0) SLR_VAL must not repeat in a 8 clock cycle period D98TL334 Figure 23. ReceiveSLAP Interface Timing The implementation must guarantee that all ac- tive SLR_Valid signals must be separated by at least 8 clock cycles. Refer to Figure 23. The SLR_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is de- fined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow. Transmit SLAP Interface The Transmit interface uses the following signals (refer to Figure 24) - SLT_REQ: byte request - SLT_FRAME: start of frame indication - SLT_DATA [1:0] data pins, a byte is transferred 2 bits at the time in 4 successive clock cycles. MSB first, odd bits on SLT_DATA [1] The logical timing diagram is shown in Figure 25. The delay between Request and the associated data byte is defined as 8 cycles. The SLT_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow and guarantee that the frame indication is as- serted when the first bits of the first DMT symbol are transferred. 08 9 1 CLOCK UNDEFINED SLT_FRAME SLT_REQUEST b7 b5 b3 b1 b6 b4 b2 b0 one byte in 4 cycles SLT_DATA(1) SLT_DATA(0) repeated each superframe/ S-frame D98TL336 11 1 02 STM_CLOCK Request may be repeated after 4 cycles Delay Request-Data equals 8 cycles UNDEFINED Figure 25. Transmit SLAP Interface Timing Diagram EXTERNAL COMPONENT (SLAVE) MODEM (MASTER) D98TL335 CLOCK DATA 2 REQUEST FRAME Figure 24. Interface Towards PHY Layer Tper Th Ti CLOCK ALL INPUTS ALL OUTPUTS Ts Thd Td D98TL337 Figure 26. InterfaceTiming STLC60135 19/25 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |