STLC60135 datasheet(12/25 Pages) STMICROELECTRONICS

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The processor interface in i960 mode

The i960 mode supports a synchronous bus inter-

face protocol.

Address and data are multiplexed. The processor

is bus master and the STLC60135 is bus slave.

Synchronous means that all signals are synchro-

nous with the input clock PCLK pin.

The bus cycles are directly started and driven by

the processor. Addresses (BE1, AD[2..15]) have

to be present before ATC asserts the ALE signal.

STLC60135 latches the address on the falling

edge of ALE signal.

The RDYB output is synchronous to PCLK.

A bus cycle consists of an Access cycle (Ta),

Wait cycles (Tw), Data cycle (Td) and Recovery

cycle (Tr).

Processor Interface Pins and Functional De-

scription i960 mode

Name

Type

Function

AD[0...15]

I/O

Multiplexed Address/Data bus

BE1

Address bit 1

ALE

Address Latch Enable

WR_RDB

Access direction: Write (1), Read (0)

PCLK

Processor Clock

CSB

Chip Select

RDYB

Bus cycle ready indication

INTB

Interrupt

Generic Interface

This interface is suitable for a number of proces-

sors using a multiplexed Address/data bus. In this

case, synchronisation of the input signals with

PCLK pin is not necessary.

Talew

D98TL327

ALE

AD(15-0)

Tavh

CSB

WRB

READY

RDB

Tavs

Tale2cs

Tcs2wr

Twr2d

Twrw

Twr2cs

Twdvd

Tdvh

Tmclk

Tcs2rdy

Tcsre

Trdy2wr

Figure 12. Generic Processor Interface Write Timing Cycle

Talew

D98TL328

ALE

AD(15-0)

Tavh

CSB

RDB

READY

WRB

Tavs

Tale2cs

Twr2d

Twrw

Trd2cs

Twdvd

Tdvh

Tmclk

Tcsrs

Tcsre

Trdy2dr

Tale2Z

Tcsrd

Figure 13. Generic Processor Interface Read Timing Cycle

STLC60135

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