 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STLC60135 数据表(PDF) 15 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLC60135 数据表(HTML) 15 Page - STMicroelectronics |
|
|
15 / 25 page  When RxEnb is asserted, the STLC60135 reads data from its internal fifo and presents it on RxData and RxSOC on each low-to-high transi- tion of RxClk, ie the ATM layer chip samples all RxData and RxSOC on the rising edge of RxSOC on the rising edge of RxClk. Pin Description Name Type Meaning Usage Remark TxClav O Transmit Cell available Signals to the ATM chip that the physical layer chip is ready to accept a complete cell Remains active for the entire cell transfer TxEnb* I Transmit Enable Signals to the STLC60135 that TxData and TxSOC are valid TxClk I Transmit Byte Clock Gives the timing signal for the transfer, generated by ATM layer chip. TxData I Transmit Data (8bits) ATM cell data, from ATM layer chip to STLC60135, byte wide. TxData [7] is the MSB. TxSOC I Transmit Start of Cell Identifies the cell boundary on TxData TxData contains the first valid byte of the cell. TxRef * I Reference Clock 8kHz clock from the ATM layer chip *Active low signal The STLC60135 samples TxData and TxSOC signals on the rising edge of TxClk, if TxEnb is asserted. TxClk, RxClk, AC electrical characteristics Symbol Parameters Min Max Unit F Clock frequency 1.5 25 MHz Tc Clock duty cycle 40 60 % Tj Clock peak to peak jitter 5 % Trf Clock rise fall time 4 ns L Load 100 pF TxData, TxSOC, AC electrical characteristics Symbol Parameters Min Max Unit T5 Input set-up time to TxClk 10 ns T6 Hold time to TxClk 1 ns L Load 100 pF RxData, RxSOC, RxClav AC electrical charac- teristics Symbol Parameters Min Max Unit T7 Input set-up time to TxClk 10 ns T8 Hold time to Tx Clk 1 ns T9 Signal going low impedance to RxClk 10 ns T10 Signal going High impedance to RxClk 0ns T11 Signal going low impedance to RxClk 1ns T12 Signal going High impedance to RxClk 1ns L Load 100 pF D98TL371 TxCLK TxSOC TxDATA TxCLAV X H1 H2 P44 P45 P46 P47 P48 X TxENB Figure 18. Timing (Utopia 1 Transmit Interface) STLC60135 15/25 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
