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STLC60135 数据表(PDF) 2 Page - STMicroelectronics |
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STLC60135 数据表(HTML) 2 Page - STMicroelectronics |
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2 / 25 page ![]() ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V Ptot Total Power Dissipation 900 1400 mW Tamb Ambient Temperature 1m/s airflow -40 85 °C The STLC60135 can be splitted up into two differ- ent sections. The physical one performs the DMT modulation, demodulation, Reed-Solomon encod- ing, bit interleaving and 4D trellis coding. The ATM section embodies framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed Solomon error corrections, with and without interleaving. The STLC60135 is controlled and programmed by an external controller (ADSL Transceiver Con- troller, ATC) that sets the programmable coeffi- cients. The firmware controls the initialization phase and carries out the consequent adaptation operations. Transient Energy Capabilities ESD ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM). The pins of the device are to be able to withstand minimum 1500V for the HBM and minimum 250V for CDM. Latch-up The maximum sink or source current from any pin is limited to 100mA to prevent latch-up. 1 2 3 5 6 4 7 8 9 10 46 11 47 48 49 50 51 135134133132 130 131 129128127126125 100 99 98 96 95 97 105 104 103 101 102 AD_3 VDD AD_2 AD_0 VSS AD_1 VDD AD_6 AD_5 AD_4 VSS SLT_DAT_F1 VSS SLT_FRAME_F SLR_VAL_F SLR_DAT_F0 SLAP_CLOCK VDD SLT_REQ_F SLT_DAT_S0 SLT_DAT_F0 SLT_DAT_S1 D98TL367B 41 42 43 44 45 136 138 139 140 141 37 38 39 40 94 93 91 90 92 SLR_DAT_F1 SLR_VAL_S SLR_DAT_S0 SLR_DAT_S1 VDD 12 13 14 15 16 AD_10 VSS AD_9 AD_7 AD_8 54 55 56 57 58 59 124 122 123 121120119118117 52 53 17 18 19 88 87 89 AD_12 VDD AD_11 VSS SLR_FRAME_F SLR_FRAME_S 86 85 83 82 84 U_TX_ADDR_0 U_TX_ADDR_1 VDD U_TX_ADDR_3 U_TX_ADDR_2 20 21 22 23 24 AD_14 AD_13 VDD VSS PCLK 25 26 27 80 79 81 BE1 VSS AD_15 U_TX_DATA_0 U_TX_DATA_1 U_TX_ADDR_4 78 77 75 74 76 VDD U_TX_DATA_2 U_TX_DATA_4 U_TX_DATA_5 U_TX_DATA_3 28 29 30 31 32 RDYB WR_RDB CSB ALE VDD 62 63 64 65 66 67 116 114 115 113112111110109 60 61 73 U_TX_DATA_6 U_TX_DATA_7 VDD 33 34 35 RESETB INTB OBC_TYPE 68 69 70 36 VSS VSS 71 72 106 107 108 137 142 143 144 Figure 2. Pin Connection STLC60135 2/25 |
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