STLC60135 datasheet(14/25 Pages) STMICROELECTRONICS

14 / 25 page

The Utopia Level 2 supports point to multipoint

configurations by introducing an addressing capa-

bility and by making distinction between polling

and selecting a device.

Utopia Level 1 Interface

The ATM forum takes the ATM layer chip as a

reference. It defines the direction from ATM to

physical layer as the Transmit direction. The di-

rection from physical layer to ATM is the Receive

direction. Figures 15 & 16 show the interconnec-

tion between ATM and PHY layer devices, the

optional signals are not supported and not

shown.

The Utopia interface transfers one byte in a sin-

gle clock cycle, as a result cells are transformed

in 53 clock cycles.

Both transmit and receive are synchronized on

clocks generated by the ATM layer chip, and no

specific relationship between receive and transmit

clocks is required.

In this mode, the STLC60135 can only support

one data flow : either interleaved or fast .

D98TL369

RxCLK

RxSOC

RxDATA

RxCLAV

P44

P45

P46

P47

P48

RxENB

Figure 17. Timing (Utopia 1 Receive Interface)

PHY

RECEIVE

CELL

RECEIVE

ATM

PHY

RxREF*

RxCLAV

RxENB*

RxCLK

RxDATA

RxSOC

D98TL330

Figure 15. ReceiveInterface

PHY

TRANSMIT

PHY

TxREF*

TxCLAV

TxENB*

TxCLK

TxDATA

TxSOC

D98TL370

CELL

TRANSMIT

ATM LAYER

Figure 16. Transmit Interface

Pin Description

Name

Type

Meaning

Usage

Remark

RxClav

Receive Cell available

Signals to the ATM chip that the

STLC60135 has a cell ready for

transfer

Remains active for the entire cell

transfer

RxEnb*

Receive Enable

Signals to the STLC60135 that the

ATM chip will sample and accept

data during next clock cycle

RxData and RxSOC could be tri-

state when RxEnb* is inactive

(high). Active low signal

RxClk

Receive Byte Clock

Gives the timing signal for the

transfer, generated by ATM layer

chip.

RxData

Receive Data (8bits)

ATM cell data, from STLC60135

chip to ATM chip, byte wide. Rx

Data [7] is the MSB.

RxSOC

Receive Start Cell

Identifies the cell boundary on

RxData

Indicate to the ATM layer chip that

RxData contains the first valid byte

of a cell.

RxRef *

Reference Clock

8 kHz clock transported over the

network

Active low signal

*Active low signal

STLC60135

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