STLC60135 datasheet(18/25 Pages) STMICROELECTRONICS

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Pin Description Utopia 2 (Transmit interface)

Name

Type

Meaning

Usage

Remark

TxClav

Transmit Cell

available

Signals to the ATM chip that the

physical layer chip is ready to

accept a cell

Remains active for the entire cell

transfer

TxEnb*

Transmit Enable

Signals to the physical layer that

TxData and TxSOC are valid

TxClk

Transmit Byte Clock

Gives the timing signal for the

transfer, generated by ATM layer

chip.

TxData

Transmit Data (8 bits)

ATM cell data, to physical layer

chip to ATM chip, byte wide.

TxSOC

Transmit Start of Cell

Identifies the cell boundary on

TxData

TxAddr

Transmit Address

(5 bits)

Use to select the port that will be

active or polled

TxRef *

Reference Clock

8kHz clock from the ATM layer chip

*Active low signal

BitStream Interface

The Bitstream interface is a proprietary point to

point interface. The STLC60135 is the bus mas-

ter of the interface. The interface is synchronous,

a common clock is used.

SLAP (Synchronous Link Access Protocol) In-

terface

The SLAP interface is a point to point bitstream

interface. The STLC60135 is the bus master of

the interface.

The interface is synchronous, a common clock

(SLAP_CLOCK) is used. The basic idea is illus-

trated in Figure 20.

The SLAP interface dumps the data of the fast

and interleaved channels on 2 separate sub inter-

faces.

The data flow from the SLAP interface must be

enabled by the Transceiver Controller. A disabled

cell interface does not dump data on its interface.

Receive SLAP Interface

The interface signals use 2 signal types: (refer to

fig. 22)

- SLR_DATA [1:0]: data pins, a byte is transferred

in 4 cycles of 2 bits. The msb are transmitted first,

odd bits are asserted on SLR_DATA [1].

- SLR_VAL: indicates the data transfer and the

byte boundary

- SLR_FRAME: indicates the start of a super-

frame

Notice 2 SLAP interfaces are supported, one for

the fast data flow, the other one for the inter-

leaved data flow.

The logic timing diagram is shown in figure 23.

EXTERNAL

COMPONENT

(SLAVE)

MODEM

(MASTER)

D98TL333

SLAP_CLOCK

DATA

VALID

FRAME

Figure 22. ReceivePath, SLAP Interface

SOURCE

RISING

CLOCK

FALLING

CLOCK

SINK

D98TL332

SLAP_CLOCK

Figure 21. Common Clock Data Transfer

STLC60135

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