STLC60135 datasheet(11/25 Pages) STMICROELECTRONICS

11 / 25 page

The DSTU schedulers execute a program, con-

trolled by program opcodes and a set of vari-

ables, the most important of which are real time

counters. The transmit and receive sequencers

are completely independent and run different pro-

grams. An independent set of variables is as-

signed to each of them. The sequencer programs

can be updated in real time.

STLC60135 interfaces

Overview

Processor Interface (ATC)

The STLC60135 is controlled and configured by

an external processor across the processor inter-

face. All programmable coefficients and parame-

ters are loaded through this path.

The ADSL initialization is also controlled by this

interface

Two interface types are supported; A generic

asynchronous interface (i.e. PowerPC or any mi-

croprocessor interface) and a specific i960 inter-

face. The choice is made by the OBC_TYPE pin.

(0 selects i960 type interface, 1 selects generic

access).

Data and addresses are multiplexed.

STLC60135 works in 16 bits data access, so ad-

dress bit 0 is not used. Address bit 1 is not multi-

plexed with data. It has its own pin : BE1

Byte acces are not supported. Access cycle read

or write are always in 16 bits data wide, ie bit ad-

dress A0 is always zero value. The interrupt re-

quest pin to the processor is INTB, and

is an

Open Drain output.

Tle STLC60135 supports both little and big en-

dian. The default feature is big endian.

D98TL324A

PCLK

CSB

ALE

RDYB

BE1

WR_RDB

Wait

ADDR

DATAin

ADD(1)

ATC samples data

(1): The RDYB output is continuously

in tri-state, except for 2 cycles

Figure 10. Processor Interface Read cycle i960 mode

STLC60135

AFE INTERFACE TO

ADSL LINE (STLC60134)

PROCESSOR

INTERFACE

(ATC)

RESET

JTAG

CLOCK

DIGITAL INTERFACE

UTOPIA/BITSTREAM INTERFACE

D98TL368A

Figure 9. STLC60135 interfaces

D98TL325A

PCLK

CSB

ALE

RDYB

BE1

WR_RDB

Wait

ADDR

DATAout

ADD(1)

STLC60135 samples data

(1): The RDYB output is continuously

in tri-state, except for 2 cycles

Figure 11. Processor Interface Write Cycle i960 mode

STLC60135

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