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STLC60135 数据表(PDF) 22 Page - STMicroelectronics

部件名 STLC60135
功能描述  TOSCA ADSL DMT TRANSCEIVER
PDF  25 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLC60135 数据表(HTML) 22 Page - STMicroelectronics

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Table 6: (continued)
Sequence
Number
Mnemonic
Pin
BS Type
61
U_TxRefB
I
63
U_RxCLK
64
U_RxSOC
65
U_RxCLAV
66
U_RxENBB
68
U_TxCLK
69
U_TxSOC
70
U_TxCLAV
71
U_TxENBB
74
U_TxData_7
I
75
U_TxData_6
I
77
U_TxData_5
I
78
U_TxData_4
I
79
U_TxData_3
I
80
U_TxData_2
I
82
U_TxData_1
I
83
U_TxData_0
I
84
U_TxADDR_4
I
85
U_TxADDR_3
I
87
U_TxADDR_2
I
88
U_TxADDR_1
I
89
U_TxADDR_0
I
90
SLR_FRAME_F
92
SLR_FRAME_S
93
SLR_DATA_S_1
94
SLR_DATA_S_0
96
SLR_DATA_S
97
SLR_DATA_F_1
98
SLR_DATA_F_0
99
SLR_VAL_F
100
SLAP_CLOCK
101
SLT_FRAME_F
103
SLT_DATA_F_1
104
SLT_DATA_F_0
105
SLT_DATA_S_1
106
SLT_DATA_S_0
107
SLT_REQ_F
110
SLT_REQ_S
111
SLT_FRAME_S
112
TDI
113
TDO
114
TMS
116
TCK
118
TRSTB
119
TESTSE
none
120
GP_OUT
O
121
PDOWN
O
123
AFRXD_0
I
124
AFRXD_1
I
125
AFRXD_2
I
126
AFRXD_3
I
128
CLWD
1
I
129
MCLK
1
C
130
CTRLDATA
1
O
132
AFTXED_0
O
133
AFTXED_0
O
135
AFTXED_0
O
136
AFTXED_0
O
138
IDDq
none
139
AFTXD_0
O
140
AFTXD_1
O
142
AFTXD_0
O
143
AFTXD_1
O
General purpose I/O register
2 general Purpose Register (0x040)
Field
Type
Position
bits
Length
Function
GP_IN
R
[0,1]
2
Sampled level
on pins GP_IN
GP_OUT
RW
[2]
1
Output level on
pins GP_OUT
bits from 3 to 15 are reserved
Reset Initialization
The STLC60135 supports two reset modes:
- A ’hardware’ reset is activated by the RESETB
pin (active low). A hard reset occurs when a low
input value is detected at the RESETB input.
The low level must be applied for at least 1ms
to guarantee a correct reset operation. All
clocks and power supplies must be stable for
200ns prior to the rising edge of the RESETB
signal.
- ’Soft’ reset activated by the controller write ac-
cess to a soft reset configuration bit. The reset
process takes less than 10000 MCLK clock cy-
cles.
ELECTRICAL SPECIFICATIONS
Generic
The values presented in the following table apply
for all inputs and/or outputs unless specified oth-
erwise. Specifically they are not influenced by the
choice between CMOS or TTL levels.
STLC60135
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