ORSPI4 datasheet(111/263 Pages) LATTICE

111 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

111

As shown in Figure 52, the basic blocks in the receive path include:

Receive SERDES Block

• CML input buffer

• Receive PLL

• 1:10 demultiplexer (DEMUX)

• Clock and Data Recovery (CDR) section

• 10b/8b decoder

• 1:4 demultiplexer and SERDES/FPGA interface

• 1:4 DEMUX

• Low speed parallel SERDES/FPGA logic interface

• Multi-channel alignment logic

Figure 52. Basic Logic Blocks, Receive Path, Single Channel (Typical Reference Clock Frequency)

Each channel provides its own received clock, received data and K-character detect signals to the FPGA logic.

Incoming data from multiple channels can be aligned using comma (/K/) characters or /A/ character (as speciﬁed

either in Fibre Channel speciﬁcations or in IEEE 802.3ae for XAUI based interfaces). If the 8b/10b decoders are

bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in this

8b/10b bypass mode.

REFCLKP

REFCLKN

REFCLK

Buffer

MUX

RCK78

78.125 MHz

RCKSEL[0:1]

Logic Common to Quad

From other 3

channels

To other 3

channels

From Control

{

PLL

PRBS Checker

CML

Buffer

1:10

DEMUX

8B/10B

Encoder

(with

bypass)

HDINP_x

HDIN_x

CDR

Byte

Align

RX SERDES Block

XAUI

State

Machine

1:4

DEMUX

(x 10)

156.25 MHz

FIFO

Multi-

Channel

Alignment

FPGA

Logic

Backplane

Serial

Link

RWCKx

78.125 MHz

Multi-Channel

Alignment Block

78.125 MHz

78.125 MHz Clock

RALIGNx[3:0]

Align Character Detect

RWBIT8x[3:0]

4 bits k-control

RWDx[31:0]

32-bit data

RSYS_CLK_#

78.125 MHz

2:1

MUX

(x40)

MRWDx[39:0]

CV_SELx

RWBIT9x[3:0]

32-bit data

4 bits k-ctrl

Synchronization

Status bits

Fibre Channel State

Machine

SRBD_x[0:9]

DEMUX

Block

SCVx

312.5 MHz

Clocks

SBYTSYNC_x

SWDSYNC_x

Note: x= [A, ..., B]

x# = [1, 2]

FPGA

Logic

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