ORSPI4 datasheet(112/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

112

Synchronization

The ORSPI4 SERDES RX logic performs four levels of synchronization on the incoming serial data stream. Each

level builds upon the previous, providing ﬁrst bit, then byte (character), then channel (32-bit word), and ﬁnally multi-

channel alignment.

Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transi-

tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL

is unable to lock to the serial data stream, it instead locks to REFCLK to stabilize the Voltage-Controlled Oscillator

(VCO), and periodically switches back to the serial data stream to again attempt synchronization. This process

continues until a valid input data stream is detected and lock is achieved. The CDR can maintain lock on data as

long as the input data stream contains an adequate data “eye” (i.e., jitter is within speciﬁcation) and the maximum

data stream run length is not exceeded.

Byte alignment occurs once valid bit alignment is achieved. The byte aligner looks for a particular 7-bit sequence

(either 0011111 or its complement, 1100000) that, has been 8b/10b encoded per Fibre Channel or IEEE

802.3.2002 speciﬁcations, only occurs in the comma (/K/) characters K28.1, K28.5 and K28.7. Byte alignment only

occurs when the ENBYSYNC_x signal for that channel is active high, and re-alignment occurs on each 7-bit

sequence encountered. However, if ENBYSYNC_x is asserted active high and no comma character is encoun-

tered, and then is brought inactive low, the channel will still perform one byte alignment operation on the next

comma character. Byte alignment occurs immediately when an alignment sequence is detected, so the lock time is

only one clock period.

Word (32-bit) alignment can occur after the Fibre Channel (XAUI_MODE_x = “0”) or XAUI (XAUI_MODE_x = “1”)

state machine has reached the in-synchronization state. In Fibre Channel mode, synchronization (WDSYNC_x =

“1”) will occur after three ordered sets of data have been received in the absence of any code violations. After this,

the next ordered set will cause the output data to be aligned such that the comma character is in the most signiﬁ-

cant byte. Thus, 32-bit word alignment has been achieved when four ordered sets have been detected. The time

required is directly dependent on comma-character density.

Once word alignment is accomplished, no further alignment occurs unless and until WDSYNC_x goes to zero and

back to one again. Comma characters that are not located in the most signiﬁcant byte position will not trigger fur-

ther re-alignment while WDSYNC_x is active. This behavior is as deﬁned by the Fibre Channel speciﬁcation. How-

ever, it means that, if the channel experiences an abrupt delay change (as could occur if an external mux performs

protection switch between two links) and if the delay change is close enough to a full character or characters that

not enough code violations are generated to cause loss of WDSYNC_x, the channel could become misaligned and

remain that way indeﬁnitely. As mentioned above, this behavior is that deﬁned by the Fibre Channel speciﬁcation.

In XAUI mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing com-

mas must be detected before synchronization is declared.

Multi (2 or 4) channel alignment (Lane alignment in XAUI mode) can be performed after 32-bit word alignment is

complete. Multi-channel alignment is described in later sections of this data sheet.

Receive CML Input Buffer and SERDES

The receiver section receives high-speed serial data at its differential CML input port. The receive input is an AC

coupled input. The received data is sent to the clock recovery section which generates a recovered clock and

retimes the data. Valid data will be received after the receive PLL has locked to the input data frequency and phase.

The received serial data is converted to a 10-bit wide parallel data by the 1:10 demultiplexer. Clock recovery is per-

formed by the SERDES block for each of the eight receive channels. This recovered data is then aligned to a 10-bit

word boundary by detecting and aligning to a comma special character. Word alignment is done for either polarity

of the comma character. The 10-bit code word is passed to the 8b/10b decoder, which provides an 8-bit byte of

data, a special character indicator bit and a SBYTSYNC_x signal (where again x is a placeholder for A,...,D). Data

from a SERDES channel is sent to the DEMUX block in 10-bit raw form or 8-bit decoded form. Accompanying this

data are the comma-character indicator (SBYTSYNC_x), link-state indicator (SWDSYNC_x), clocks (SRBC0_x,

and SRBC1_x), and code-violation indicator (SCVx). The two internal clocks operated at twice the reference clock

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