M32CSLASH8A datasheet(52/372 Pages) RENESAS

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M32C/8A Group

5. Reset

Rev.1.00

Jul 15, 2007

Page 35 of 352

REJ09B0385-0100

Table 5.1

Pin States while RESET Pin is Held “L”(2)

NOTES:

1. Ports P11 to P15 are provided in the 144-pin package only.

2. The availability of the pull-up resistors is undefined until the internal supply voltage stabilizes.

3. These pin states are defined after the power is turned on and the internal supply voltage stabilizes. Until then,

the pin states are undefined.

5.2

Hardware Reset 2 (Vdet3 detection function)

Pins, CPU, and SFRs are reset by the Vdet3 detection function, when the voltage applied to the VCC1 pin drops to

Vdet3 (V) or below. The states of the pins, CPU, and SFRs after reset are the same as the hardware reset 1. Refer

to 6. Power Supply Voltage Detection Function for details on Vdet3 detection function.

5.3

Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU is reset), the MCU resets the CPU, SFRs, ports, and I/O

pins for peripheral functions. And then the MCU executes a program in an address indicated by the reset vector.

Set the PM03 bit to 1 while the main clock is selected as the clock source for the CPU clock and the main clock

oscillation is stable.

The software reset does not reset the following SFRs; bits PM01 and PM11 in the PM0 register, the WDC5 bit in

the WDC register, and the TCSPR register.

Processor mode remains unchanged since bits PM01 and PM00 are not reset.

5.4

Watchdog Timer Reset

When the CM06 bit in the CM0 register is set to 1 (reset) and the watchdog timer underflows, the MCU resets the

CPU, SFRs, ports, and I/O pins for peripheral functions. And then the MCU executes a program in an address

indicated by the reset vector.

The watchdog timer reset does not reset the following SFRs; bits PM01 and PM11 in the PM0 register, the WDC5

bit in the WDC register, and the TCSPR register.

Processor mode remains unchanged since bits PM01 and PM00 are not reset.

Pin Name

Microprocessor Mode

CNVSS = “H”

BYTE = “L”

BYTE = “H”

Data input (high-impedance)

Input port (high-impedance)

P2 to P4

Address output (undefined)

P5_0

WR signal output (“H”)(3)

P5_1

BHE signal output (“H”)

P5_2

RD signal output (“H”)(3)

P5_3

BCLK output(3)

P5_4

HLDA signal output (output level depends on an input level to

the HOLD pin)(3)

P5_5

HOLD signal input (high-impedance)

P5_6

“H” signal output(3)

P5_7

RDY signal input (high-impedance)

P6 to P15(1)

Input port (high-impedance)

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