M32CSLASH8A datasheet(92/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 75 of 352

REJ09B0385-0100

Figure 9.6

PLC0 Register, PLC1 Register

b6 b5 b4

PLL Control Register 0 (1, 2, 5)

Symbol

PLC0

Address

0026h

Bit Symbol

Bit Name

PLC00

After Reset

0001 X010b

NOTES:

1. Set the PLC0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. If the PM21 bit in the PM2 register is set to 1 (disables a clock chang), a write to the PLC0 register has no effect.

3. Set bits PLC02 to PLC00 while the PLC07 bit is 0. Bits PLC02 to PLC00 can be written only once.

4. Enter wait mode or stop mode after the CM17 bit is set to 0 (main clock as CPU clock source) and then the PLC07 bit to 0.

5. Set registers PLC0 and PLC1 simultaneously in 16-bit units .

Function

Programmable counter

select bits(3)

PLC01

PLC02

The VCO clock is the main clock multiplied by

the following variables.

b2 b1 b0

0 1 1: Multiply-by-6

1 0 0: Multiply-by-8

Do not set to values other than the above

−

(b3)

−

(b4)

−

(b5)

Reserved bit

Set to 1

−

(b6)

PLC07

Reserved bit

Set to 0

0: PLL stops

1: PLL runs

Operation enable bit(4)

−

NOTES:

1. Set the PLC1 register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the the PLC1 register has no effect.

3. Set the PLC1 register while the PLC07 bit is 0 (PLL stopped).The PLC1 register can be written only once.

4. Set registers PLC0 and PLC1 simultaneously in 16-bit units.

Read as undefined value

Reserved bit

b7 b6 b5 b4

PLL Control Register 1(1, 2, 3, 4)

Bit Symbol

Bit Name

−

(b0)

Function

Reserved bit

−

(b1)

Reserved bit

0 0 0

1 0

PLC12

0: Divide-by-2

1: Divide-by-3

PLL clock division select bit

−

(b3)

Reserved bit

−

(b4)

−

Read as undefined value

Reserved bit

−

(b7-b5)

Reserved bits

Set to 0

Set to 1

Set to 0

Syambol

PLC1

Address

0027h

After Reset

000X 0000b

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