M32CSLASH8A datasheet(98/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 81 of 352

REJ09B0385-0100

Figure 9.11

Procedure to Switch from On-chip Oscillator Clock to Main Clock

9.1.4

PLL Clock

The PLL frequency synthesizer generates the PLL clock by multiplying the main clock. The PLL clock can be

used as the clock source for the CPU clock and peripheral function clocks.

The PLL frequency synthesizer is stopped after reset. When the PLC07 bit in the PLC0 register is set to 1 (PLL

runs), the PLL frequency synthesizer starts operating. Waiting time, tsu(PLL), is required before the PLL clock

is stabilized.

The PLL clock is the VCO clock divided by either 2 or 3. When the PLL clock is used as the clock source for

the CPU clock or peripheral function clocks, set each bit as shown in Table 9.3. Figure 9.12 shows the

procedure to use the PLL clock as the CPU clock source.

Set the CM17 bit in the CM1 register to 0 (main clock as CPU clock source) and the PLC07 bit to 0 (PLL stops)

before stopping the CPU clock or the main clock.

Start

End

PRCR register: PRC0 bit = 1

Verified several times?

0 (Main clock oscillates)

MCD register: bits MCD4 to MCD0 = 01000b

CM2 register: CM22 bit = 0

CM2 register: CM21 bit = 0

PRC0 bit = 0

YES

1 (Main clock stops)

Divide-by-8 mode

Loss of the main clock is not detected

Select the main clock as the CPU clock source

Disable writing to registers associated with clocks

Enable writing to registers associated with clocks

Read the CM23 bit in the

CM2 register

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