M32CSLASH8A datasheet(85/372 Pages) RENESAS

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M32C/8A Group

8. Bus

Rev.1.00

Jul 15, 2007

Page 68 of 352

REJ09B0385-0100

Figure 8.14

External Bus Timing with Page Mode Control Function

FFF00Ch

FFF008h

FFF001h

FFF000h

3φ + 3φ

CS0 (CE)

1φ + 2φ

BCLK

Address

Data

RD (OE)

FFF002h

1φ + 2φ

FFF007h

1φ + 2φ

FFF008h

3φ + 3φ

FFF009h

1φ + 2φ

If the MCU accesses data in other than the eight-byte block of consecutive addresses, the page mode controlled access

is started over from the first bus access.

Set using bits PWCR106 to PWCR104

Set using bits EWCR34 to EWCR30

The above applies under the following conditions:

- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).

- The DS3 bit in the DS regiter is set to 0 (8 bits wide).

- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3φ + 3φ).

- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).

- Bits PWCR106 to PWCR104 are set to 010b (1φ + 2φ).

- The PWCR107 bit is set to 1 (page mode control enabled).

FFF002h

FFF000h

3φ + 3φ

CS0 (CE)

1φ + 2φ

BCLK

Address

Data

RD (OE)

FFF004h

1φ + 2φ

FFF006h

3φ + 3φ

FFF00Ah

1φ + 2φ

The above applies under the following conditions:

- Bits PM11 and PM10 in the PM1 register are set to 11b (mode 3).

- The DS3 bit in the DS regiter is set to 1 (16 bits wide).

- Bits EWCR34 to EWCR30 in the EWCR3 register are set to 10011b (3φ + 3φ).

- The EWCR36 bit is set to 0 (add no recovery cycle when accessing external space 3).

- Bits PWCR106 to PWCR104 are set to 010b (1φ + 2φ).

- The PWCR107 bit is set to 1 (page mode control enabled).

1φ + 2φ

Set using bits PWCR106 to PWCR104

Set using bits EWCR34 to EWCR30

8-bit data bus width

16-bit data bus width

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