M32CSLASH8A datasheet(93/372 Pages) RENESAS

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M32C/8A Group

9. Clock Generation Circuits

Rev.1.00

Jul 15, 2007

Page 76 of 352

REJ09B0385-0100

Figure 9.7

PM2 Register

b7 b6 b5 b4

Processor Mode Register 2(1)

Symbol

PM2

Address

0013h

Bit Symbol

Bit Name

−

(b0)

After Reset

00h

NOTES:

1. Set the PM2 register after the PRC1 bit in the PRCR register is set to 1 (write enable).

2. Once bits PM22 and PM21 are set to 1, they cannot be set to 0 by program.

3. When the PM21 bit is set to 1,

• the CPU clock does not stop, even if the WAIT instruction is executed;

• writes to the following bits have no effect.

- the CM02 bit in the CM0 register

- the CM05 bit in the CM0 register

- the CM07 bit in the CM0 register (CPU clock source is not changed)

- the CM10 bit in the CM1 register (the MCU does not enter stop mode)

- the CM17 bit in the CM1 register (CPU clock source is not changed)

- the CM20 bit in the CM2 register (oscillation stop detect function setting is not changed)

- all bits in registers PLC0 and PLC1 (PLL frequency synthesizer setting is not changed)

4. When the PM22 bit is set to 1,

• the on-chip oscillator starts oscillating and the on-chip oscillator clock becomes the count source for the watchdog timer;

• write to the CM10 bit in the CM1 register is disabled (writing a 1 has no effect and the MCU does not enter stop mode);

• the watchdog timer keeps operating when the MCU is in wait mode or in hold state.

Function

b7 b6

0 0: Clock selected by the CM21 bit

0 1: XIN clock (fXIND)

1 0: On-chip oscillator clock (fROC)

1 1: Do not set to this value

Reserved bit

PM21

PM22

System clock protect bit(2, 3)

0: Protects a clock by the PRCR register

1: Disables a clock change

−

(b5-b3)

WDT count source protect bit(2, 4)

Set to 0

PM26

f2n clock source select bits

PM27

Reserved bits

Set to 0

0: CPU clock as count source for the watchdog

timer

1: On-chip oscillator clock as count source for

the watchdog timer

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