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M32C/86 数据表(PDF) 68 Page - Renesas Technology Corp |
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M32C/86 数据表(HTML) 68 Page - Renesas Technology Corp |
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68 / 505 page ![]() Page 45 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 6. Voltage Detection Circuit ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figure 6.4 D4INT Register 0 0 : CPU clock divided by 8 0 1 : CPU clock divided by 16 1 0 : CPU clock divided by 32 1 1 : CPU clock divided by 64 NOTES: 1. Set the D4INT registers after the PRC3 bit in the PRCR register is set to "1" (write enable). 2. The D40 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). Use the following procedure to set the D40 bit to "1": (1) Set the VC27 bit to "1" (2) Wait td(E-A) ms to start operating the voltage detection circuit (3) Wait required sampling time (see Table 6.2) (4) Set the D40 bit to "1" 3. When exiting stop mode using the low voltage detection circuit again after having already done so, set the D41 bit to "1" after setting it to "0". 4. The D42 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). The D42 bit is set to "0" when the VC27 bit is set to "0" (low voltage detection circuit disabled). 5. The bit is set to "0" by a program. (It remains unchanged even if it is set to "1".) 6. The D4INT register in M32C/86T cannot be used. Symbol Address After Reset D4INT 002F16 0016 Low Voltage Detection Interrupt Register(1,6) RW RW RW RW RW RW RW b5 b4 0: Disables the interrupt 1: Enables the interrupt 0: Disabled (cannot use the low voltage detection interrupt to exit stop/wait mode) 1: Enabled (can use the low voltage detection interrupt to exit stop/wait mode) 0: Not detected 1: Detects above or below Vdet4 0: Not detected 1: Detected D40 D41 D42 D43 WDT Overflow Detect Flag(5) Voltage Change Detect Flag(4, 5) Stop/Wait Mode Deactivation Control Bit(3) DF0 DF1 (b7 - b6) Bit Name Function Bit Symbol Sampling Clock Select Bit Low Voltage Detection Interrupt Enable Bit(2) Reserved Bit When read, its content is indeterminate RO b7 b6 b5 b4 b3 b2 b1 b0 |
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