M32CSLASH86 datasheet(99/505 Pages) RENESAS

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Page 76

9. Clock Generation Circuit

)

(

Figure 9.5 CM2 Register

CM20

CM21

CM22

CM23

(b7 - b4)

Oscillation Stop Detection Register(1)

CPU Clock

Select Bit 2(3, 4)

Oscillation Stop Detection

Enable Bit(2)

Main Clock Monitor

Flag(6)

Oscillation Stop Detection

Flag(5)

Reserved Bit

0: Main clock oscillates

1: Main clock stops

0: Clock selected by the CM17 bit

1: On-chip oscillator clock

0: Main clock does not stop

1: Detects a main clock stop

0: Disables oscillation stop detect function

1: Enables oscillation stop detect function

Set to "0"

Symbol

Address

After Reset

CM2

000D16

0016

Function

Bit Name

Bit

Symbol

NOTES:

1. Rewrite the CM2 register after the PRC0 bit in the PRCR register is set to "1" (write enable).

2. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM20 bit setting does not

change when written.

3. When a main clock oscillation stop is detected while the CM20 bit is set to "1", the CM21 bit is set to "1".

Although the main clock starts oscillating, the CM21 bit is not set to "0". If the main clock is used as a

CPU clock source after the main clock resumes oscillating, set the CM21 bit to "0" by program.

4. When the CM20 bit is set to "1" and the CM22 bit is set to "1", do not set the CM21 bit to "0".

5. When a main clock stop is detected, the CM22 bit is set to "1". The CM22 bit can only be set to "0", not

"1", by program.

If the CM22 bit is set to "0" by program while the main clock stops, the CM22 bit cannot be set to "1"

until the next main clock stop is detected.

6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop

detection interrupt is generated.

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