M32CSLASH86 datasheet(96/505 Pages) RENESAS

96 / 505 page

Page 73

9. Clock Generation Circuit

)

(

Figure 9.2 CM0 Register

Symbol

Address

After Reset

CM0

000616

0000 10002

System Clock Control Register 0(1)

CM00

CM01

CM02

Clock Output Function

Select Bit(2)

In Wait Mode, Peripheral

Function Clock Stop Bit(9)

Port XC Switch Bit

Main Clock (XIN-XOUT)

Stop Bit(5, 9)

CM04

CM05

CM06

CM07

Function

Bit Name

Bit

Symbol

0 : Main clock oscillates

1 : Main clock stops(6)

0 0 : I/O port P53

0 1 : Outputs fC

1 0 : Outputs f8

1 1 : Outputs f32

0 : I/O port function

1 : XCIN-XCOUT oscillation function(4)

XCIN-XCOUT Drive

Capacity Select Bit

(11)

Watchdog Timer

Function Select Bit

CPU Clock Select

Bit 0(8, 9, 10)

0: Clock selected by the CM21 bit

divided by MCD register setting

1: Sub clock

0 : Watchdog timer interrupt

1 : Reset(7)

NOTES:

1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable).

2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 and CM00 bits to

"002". When the PM15 and PM14 bits in the PM1 register are set to "012" (ALE output to P53), set the

CM01 and CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 and

CM00 bits) in microprocessor or memory expansion mode, and the CM01 and CM00 bits are set to

"002", an "L" signal is output from port P53 (port P53 does not function as an I/O port).

3. fc32 does not stop running. When the CM02 bit is set to "1", the PLL clock cannot be used in wait

mode.

4. When setting the CM04 bit is set to "1", set the PD8_7 and PD8_6 bits in the PD8 register to "002"

(port P87 and P86 in input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up).

5. When entering low-power consumption mode or on-chip oscillator low-power consumption mode, the

CM05 bit stops running the main clock. The CM05 bit cannot detect whether the main clock stops or

not. To stop running the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable

sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock).

When the CM05 bit is set to "1", the clock applied to XOUT becomes "H". The built-in feedback resistor

remains ON. XIN is pulled up to XOUT ("H" level) via the feedback resistor.

6. When the CM05 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"

(divide-by-8 mode). In on-chip oscillation mode, the MCD4 to MCD0 bits are not set to "010002" even

if the CM05 bit terminates XIN-XOUT.

7. Once the CM06 bit is set to "1", it cannot be set to "0" by program.

8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0".

After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1".

Do not set the CM07 bit and CM04 or CM05 bit simultaneously.

9. When the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM02, CM05 and

CM07 bits do not change even when written.

10. After the CM07 bit is set to "0", set the PM21 bit to "1".

11. When stop mode is entered, the CM03 bit is set to "1".

b1 b0

0 : Peripheral clock does not stop in

wait mode

1 : Peripheral clock stops in wait

mode(3)

CM03

0 : Low

1 : High

M32C/86 数据表(PDF) 96 Page - Renesas Technology Corp

M32C/86 数据表(HTML) 96 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载