M32CSLASH86 datasheet(81/505 Pages) RENESAS

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Page 58

8. Bus

)

(

Figure 8.2 Address Bus and Chip-Select Signal Outputs (Separate Bus)

Example 1:

When the microcomputer accesses the external

space j specified by another chip-select signal in the

next cycle after having accessed the external space i,

both address bus and chip-select signal change.

NOTES:

1. The above applies to the address bus and chip-select signal in two consecutive cycles.

By combining these examples, a chip-select signal extended by two or more cycles may be output.

Data Bus

Address Bus

Chip-Select Signal

CSk

Access

External

Space i

Chip-Select Signal

CSp

Access

External

Space j

Address

Data

Example 2:

When the microcomputer accesses the SFR or the

internal ROM/RAM area in the next cycle after

having accessed an external space, the chip-select

signal changes but the address bus does not.

Example 3:

When the microcomputer accesses the space i

specified by the same chip-select signal in the next

cycle after having accessed the external space i,

the address bus changes but the chip-select signal

does not.

Data Bus

Address Bus

Chip-Select Signal

CSk

Data

Address

Data Bus

Address Bus

Chip-Select Signal

CSk

Data

Address

Access

External

Space

No Access

Access

External

Space i

Access

External

Space i

Data Bus

Address Bus

Chip-Select Signal

CSk

Data

Address

Example 4:

When the microcomputer does not access any

space in the next cycle after having accessed an

external space (no pre-fetch of an instruction is

generated), neither address bus nor chip-select

signal changes.

Data

Access

External

Space

Access SFR,

Internal

ROM/RAM

Area

i = 0 to 3

k = 0 to 3

j = 0 to 3, excluding i

p= 0 to 3, excluding k

(See Figure 7.3 for i, j and p, k)

k = 0 to 3

i = 0 to 3

k = 0 to 3

(See Figure 7.3 for i and k)

k = 0 to 3

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