M32CSLASH86 datasheet(97/505 Pages) RENESAS

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Page 74

9. Clock Generation Circuit

)

(

Figure 9.3 CM1 Register

CM10

(b4 - b1)

(b5)

(b6)

CM17

System Clock Control Register 1(1)

Reserved Bit

All Clock Stop Control

Bit(2, 5)

Reserved Bit

CPU Clock Select

Bit 1(4,5)

Set to "0"

Set to "1"

0 : Clock oscillates

1 : All clocks stop (stop mode)(3)

0 : Main clock

1 : PLL clock

Symbol

Address

After Reset

CM1

000716

0010 00002

Function

Bit Name

Bit

Symbol

NOTES:

1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enable).

2. When the CM10 bit is set to "1", the clock applied to XOUT becomes "H" and the built-in feedback

resistor is disabled. XIN, XCIN and XCOUT are placed in high-impedance states.

3. When the CM10 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002"

(divide-by-8 mode). When the CM20 bit is set to "1" (oscillation stop detect function enabled) or the

CM21 bit to "1" (on-chip oscillator selected), do not set the CM10 bit to "1".

4. The CM17 bit setting is enabled only when the CM21 bit in the CM2 register is set to "0". Use the

procedure shown in Figure 9.12 to set the CM17 bit to "1".

5. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM10 and CM17 bits do

not change when written.

If the PM22 bit in the PM2 register is set to "1" (on-chip oscillator clock as watchdog timer count

source), the CM10 bit setting does not change when written.

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