M32CSLASH86 datasheet(100/505 Pages) RENESAS

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Page 77

9. Clock Generation Circuit

)

(

Figure 9.6 TCSPR and CPSRF Registers

CNT0

CNT1

CNT2

CNT3

(b6 - b4)

CST

NOTES:

1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "0".

2. Value of the TCSPR register is not reset by software reset or watchdog timer reset.

Count Source Prescaler Register

Division Rate

Select Bit(1)

Operation Enable Bit

Reserved Bit

0: Divider stops

1: Divider starts

If setting value is n, f2n is the

main clock, on-chip oscillator clock

or PLL clock divided by 2n.

When n is set to "0", no division is

selected.

Symbol

Address

After Reset(2)

TCSPR

035F16

0XXX 00002

Function

Bit Name

Bit

Symbol

CPSR

(b6 - b0)

Clock Prescaler Reset Flag

Clock Prescaler Reset

Flag

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Symbol

Address

After Reset

CPSRF

034116

0XXX XXXX2

Function

Bit Name

Bit

Symbol

When the CPSR bit is set to "1", fC

divided by 32 is reset.

When read, its content is "0".

When read,

its content is indeterminate

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