M32CSLASH86 datasheet(98/505 Pages) RENESAS

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Page 75

9. Clock Generation Circuit

)

(

Figure 9.4 MCD Register

MCD0

MCD1

MCD2

MCD3

MCD4

(b7 - b5)

Main Clock Division Register(1)

Main Clock Division

Select Bit(2, 4)

1 0 0 1 0 : Divide-by-1(no division)

mode

0 0 0 1 0 : Divide-by-2 mode

0 0 0 1 1 : Divide-by-3 mode

0 0 1 0 0 : Divide-by-4 mode

0 0 1 1 0 : Divide-by-6 mode

0 1 0 0 0 : Divide-by-8 mode

0 1 0 1 0 : Divide-by-10 mode

0 1 1 0 0 : Divide-by-12 mode

0 1 1 1 0 : Divide-by-14 mode

0 0 0 0 0 : Divide-by-16 mode

Symbol

Address

After Reset

MCD

000C16

XXX0 10002

Function

Bit Name

Bit

Symbol

NOTES:

1. Rewrite the MCD register after the PRC0 bit in the PRCR register is set to "1" (write enable).

2. When the microcomputer enters stop mode or low-power consumption mode, the MCD4 to MCD0 bits

are set to "010002".

The MCD4 to MCD0 bits are not set to "010002" even if the CM05 bit in the CM0 register is set to "1"

(XIN-XOUT stopped) in on-chip oscillator mode.

3. Bit combinations cannot be set not listed above.

4. Access CAN-associated register addresses after setting the MCD4 to MCD0 bits are set to "100102",

when the PM24 bit in the PM2 register is set to "0" (clock selected by the CM07 bit).

(Note 3)

b4 b3 b2 b1 b0

Reserved Bit

When read,

its content is indeterminate

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