M32CSLASH86 datasheet(101/505 Pages) RENESAS

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Page 78

9. Clock Generation Circuit

)

(

PLC12

(b0)

(b1)

(b3)

(b4)

Function

PLL Control Register 1(1, 2, 3, 4)

Reserved Bit

0 : Divide-by-2

1 : Divide-by-3

Set to "0"

PLL Clock Division

Switch Bit

(b7 - b5)

Bit Name

Bit

Symbol

Address

After Reset

PLC1

002716

000X 00002

Reserved Bit

Set to "1"

Reserved Bit

Set to "0"

NOTES:

1. Rewrite the PLC1 register after the PRC0 bit in the PRCR register is set to "1" (write enable).

2. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the PLC1 register does not

change when written.

3. Set the PLC1 register when the PLC07 bit is set to "0" (PLL off).

4. Set the PLC0 and PLC1 registers simultaneously in 16-bit units.

When read,

its content is indeterminate

Figure 9.7 PLC0 and PLC1 Registers

PLC00

PLC01

PLC02

(b3)

(b4)

(b5)

(b6)

PLC07

Function

PLL Control Register 0(1, 2, 5)

Programmable Counter

Select Bit(3)

Reserved Bit

Operation Enable Bit(4)

0: PLL is Off

1: PLL is On

Set to "1"

Reserved Bit

Set to "0"

Reserved Bit

Set to "1"

Bit Name

Bit

Symbol

Address

After Reset

PLC0

002616

0001 X0102

NOTES:

1. Rewrite the PLC0 register after the PRC0 bit in the PRCR register is set to "1" (write enable).

2. If the PM21 bit in the PM2 register is set to "1" (clock change disable), the PLC0 register setting does

not change when written.

3. Set the PLC02 to PLC00 bits when the PLC07 bit is set to "0". Once these bits are set, they cannot be

changed.

4. Set the CM17 bit in the CM1 register to "0" (main clock as CPU clock source) and the PLC07 bit to "0"

before entering wait or stop mode.

5. Set the PLC0 and PLC1 registers simultaneously in 16-bit units.

0 1 1 : Multiply-by-6

1 0 0 : Multiply-by-8

Do not set to values other than the above

b2 b1 b0

When read,

its content is indeterminate

101

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