M32CSLASH86 datasheet(122/505 Pages) RENESAS

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11. Interrupts

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11.3 Hardware Interrupts

Special interrupts and peripheral function interrupts are available as hardware interrupts.

11.3.1 Special Interrupts

Special interrupts are non-maskable interrupts.

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11.3.1.1 NMI Interrupt

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The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal

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to a low-level ("L") signal. Refer to 11.8 NMI Interrupt for details.

11.3.1.2 Watchdog Timer Interrupt

The watchdog timer interrupt occurs when a count source of the watchdog timer underflows. Refer to

12. Watchdog Timer for details.

11.3.1.3 Oscillation Stop Detection Interrupt

The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscilla-

tion stop. Refer to 9. Clock Generation Circuit for details.

11.3.1.4 Low Voltage Detection Interrupt

The low voltage detection interrupt occurs when the voltage applied to VCC is above or below Vdet4.

Refer to 6. Voltage Detection Circuit for details.

NOTES:

1. Low voltage detection interrupt cannot be used in M32C/86T.

11.3.1.5 Single-Step Interrupt

Do not use the single-step interrupt. For development support tool only.

11.3.1.6 Address Match Interrupt

The address match interrupt occurs immediately before executing an instruction that is stored into an

address indicated by the RMADi register (i=0 to 7) when the AIERi bit in the AIER register is set to "1"

(address match interrupt enabled). Set the starting address of the instruction in the RMADi register.

The address match interrupt does not occur when a table data or addresses of the instruction other

than the starting address, if the instruction has multiple addresses, is set. Refer to 11.10 Address

Match Interrupt for details.

11.3.2 Peripheral Function Interrupt

The peripheral function interrupt occurs when a request from the peripheral functions in the microcom-

puter is acknowledged. The peripheral function interrupts and software interrupt numbers 8 to 49, 52

to 54 and 57 for the INT instruction use the same interrupt vector table. The peripheral function inter-

rupt is a maskable interrupt.

See Table 11.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each

function for details.

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