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M32C/86 数据表(PDF) 233 Page - Renesas Technology Corp |
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M32C/86 数据表(HTML) 233 Page - Renesas Technology Corp |
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233 / 505 page  Page 210 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (Special Function) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M (4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1" (3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0" SDAi SCLi Receive interrupt (DMA request) Transmit interrupt SDAi SCLi i=0 to 4 IICM2 : Bit in the UiSMR2 register CKPH : Bit in the UiSMR3 regiser The above timing applies to the following setting : • The CKDIR bit in the UiMR register is set to "1" (slave) (1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay) D6 D5 D4 D3 D2 D1 D8 (ACK or NACK) D7 SDAi SCLi D0 ACK interrupt (DMA request) or NACK interrupt (2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay) SDAi SCLi 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit b15 ••• b9 b8 b7 b0 D8 Contents of the UiRB register b15 ••• b9 b8 b7 b0 b15 ••• b9 b8 b7 b0 b15 ••• b9 b8 b7 b0 b15 ••• b9 b8 b7 b0 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D7 D0 ACK interrupt (DMA request) or NACK interrupt D8 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit D8 (ACK or NACK) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit Data is transferred to the UiRB register Data is transferred to the UiRB register Data is transferred to the UiRB register Receive interrupt (DMA request) Transmit interrupt Data is transferred to the UiRB register Data is transferred to the UiRB register Contents of the UiRB register Contents of the UiRB register Contents of the UiRB register Contents of the UiRB register Figure 17.20 SCLi Timing |
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