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M32C/86 数据表(PDF) 297 Page - Renesas Technology Corp |
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M32C/86 数据表(HTML) 297 Page - Renesas Technology Corp |
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297 / 505 page  Page 274 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O (Base Timer) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Bit 15 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" (1) When the IT bit in the G1BCR0 register is set to "0" (bit 15 in the base timer overflows) Bit 14 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" (2) When the IT bit is set to "1" (bit 14 in the base timer overflows) FFFF16 800016 Base Timer Base Timer 000016 400016 C00016 FFFF16 800016 Base Timer The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) (3) When the RST1 bit in the G1BCR1 register is set to "1" (the base timer is reset by matching with the G1PO0 register) 800016 000016 800216 The above applies to the following conditions: • Value of G1PO0 register: "800016" • The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) Figure 22.11 Counter Increment/Decrement Mode |
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