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M32C/86 数据表(PDF) 310 Page - Renesas Technology Corp

部件名 M32C/86
功能描述  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M32C/86 数据表(HTML) 310 Page - Renesas Technology Corp

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Page 287
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22. Intelligent I/O (Waveform Generating Function)
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Table 22.11 SR Waveform Output Mode Specifications (Continued)
Item
Specification
Waveform Output Start Condition(5) The IFEq bit (q=0 to 7) in the G1FE register is set to "1" (channel q function
enabled)
Waveform Output Stop Condition
The IFEq bit is set to "0" (channel q function disabled)
Interrupt Request
The PO1jR bit in the interrupt request register is set to "1" (interrupt requested)
when the value of the base timer matches that of the G1POj register.
The PO1kR bit in the interrupt request register is set to "1" (imterrupt requested)
when the value of the base timer matches that of the G1POk register. (See
Figure 11.14)
OUTC1j Pin
Pulse signal output pin
Selectable Function
• Default value set function: Set starting waveform output level
• Inversed output function
Waveform output level is inversed to provide a waveform from the OUTC1j pin
NOTES:
5. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected).



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