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M38C31M7AXXXFS 数据表(PDF) 33 Page - Renesas Technology Corp |
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M38C31M7AXXXFS 数据表(HTML) 33 Page - Renesas Technology Corp |
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33 / 224 page ![]() 38C3 Group User’s Manual HARDWARE 1-18 Fig. 14 Port block diagram (3) FUNCTIONAL DESCRIPTION (14)Port P70 Direction register Data bus Port latch Port selection • pull-up control Oscillator Port P70 (15)Port P71 Direction register Data bus Port Xc switch bit Port latch Port selection • pull-up control Sub-clock generating circuit input (16)COM0–COM3 VL3 VL2 VL1 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. (13)Port P6 Analog input pin selection bit A-D conversion input Data bus Port latch Direction register Pull-up control (17)Port P8 Key input (key-on wake-up) interrupt input Data bus Direction register Port latch Pull-up control P-channel output disable bit Port Xc switch bit Port Xc switch bit |
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