M38C31M7AXXXFS datasheet(13/224 Pages) RENESAS

13 / 224 page

38C3 Group User’s Manual

List of figures

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics .......................................... 3-18

Fig. 3.1.2 Timing chart ................................................................................................................ 3-19

Fig. 3.2.1 Power source current standard characteristics ...................................................... 3-20

Fig. 3.2.2 Power source current standard characteristics (in wait mode) ........................... 3-20

Fig. 3.2.3 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C) .... 3-21

Fig. 3.2.4 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (90 °C) .... 3-21

Fig. 3.2.5 CMOS output port (P0, P1, P2, P3) P-channel side characteristics (25 °C) .... 3-22

Fig. 3.2.6 CMOS output port (P0, P1, P2, P3) N-channel side characteristics (90 °C) ... 3-22

Fig. 3.2.7 CMOS output port (P4, P50, P52–P57, P6, P70, P71, P8) P-channel side characteristics

(25 °C) .......................................................................................................................... 3-23

Fig. 3.2.8 CMOS output port (P4, P50, P52–P57, P6, P70, P71, P8) P-channel side characteristics

(90 °C) .......................................................................................................................... 3-23

Fig. 3.2.9 CMOS output port (P4, P52–P57, P6, P70, P71) N-channel side characteristics (25 °C)

........................................................................................................................................................ 3-24

Fig. 3.2.10 CMOS output port (P4, P52–P57, P6, P70, P71) N-channel side characteristics

(90 °C) ....................................................................................................................... 3-24

Fig. 3.2.11 CMOS output port (P50, P8) N-channel side characteristics (25 °C) ............... 3-25

Fig. 3.2.12 CMOS output port (P50, P8) N-channel side characteristics (90 °C) ............... 3-25

Fig. 3.3.1 Sequence of switch detection edge ......................................................................... 3-26

Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-26

Fig. 3.3.3 Structure of interrupt control register 2 .................................................................. 3-27

Fig. 3.3.4 PWM output and IGBT output (1) ............................................................................ 3-27

Fig. 3.3.5 PWM output and IGBT output (2) ............................................................................ 3-28

Fig. 3.3.6 PWM output and IGBT output (3) ............................................................................ 3-28

Fig. 3.4.1 Selection of packages ............................................................................................... 3-31

Fig. 3.4.2 Wiring for the RESET pin ......................................................................................... 3-31

Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-32

Fig. 3.4.4 Wiring for the VPP pin of the One Time PROM and the EPROM version ......... 3-33

Fig. 3.4.5 Bypass capacitor across the VSS line and the VCC line ........................................ 3-33

Fig. 3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-34

Fig. 3.4.7 Wiring for a large current signal line ...................................................................... 3-34

Fig. 3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-35

Fig. 3.4.9 VSS pattern on the underside of an oscillator ........................................................ 3-35

Fig. 3.4.10 Setup for I/O ports ................................................................................................... 3-36

Fig. 3.4.11 Watchdog timer by software ................................................................................... 3-37

Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-38

Fig. 3.5.2 Structure of Port P0 direction register and Port P1 direction register ............... 3-38

Fig. 3.5.3 Structure of Port Pi direction register ..................................................................... 3-39

Fig. 3.5.4 Structure of Port P7 ................................................................................................... 3-39

Fig. 3.5.5 Structure of Port P7 direction register .................................................................... 3-40

Fig. 3.5.6 Structure of PULL register A .................................................................................... 3-40

Fig. 3.5.7 Structure of PULL register B .................................................................................... 3-41

Fig. 3.5.8 Structure of Port P8 output selection register ....................................................... 3-42

Fig. 3.5.9 Structure of Serial I/O control register 1 ................................................................ 3-43

Fig. 3.5.10 Structure of Serial I/O control register 2 .............................................................. 3-44

Fig. 3.5.11 Structure of Serial I/O register ............................................................................... 3-44

Fig. 3.5.12 Structure of Timer i ................................................................................................. 3-45

Fig. 3.5.13 Structure of Timer 2 ................................................................................................ 3-45

Fig. 3.5.14 Structure of Timer 6 PWM register ....................................................................... 3-46

Fig. 3.5.15 Structure of Timer 12 mode register ..................................................................... 3-46

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