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M38C31M7AXXXFS 数据表(PDF) 35 Page - Renesas Technology Corp

部件名 M38C31M7AXXXFS
功能描述  8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
PDF  224 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M38C31M7AXXXFS 数据表(HTML) 35 Page - Renesas Technology Corp

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38C3 Group User’s Manual
HARDWARE
1-20
Interrupt Source
Reset (Note 2)
INT0
INT1
INT2
Serial I/O
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
CNTR1
Key input (Key-
on wake-up)
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses (Note 1)
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At detection of either rising or falling edge of
INT2 input
At completion of serial I/O data transmit/re-
ceive
At timer A underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At falling of port P8 (at input) input logical level
AND
At completion of A-D conversion
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Valid when A-D conversion interrupt
is selected
Non-maskable software interrupt
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 8 Interrupt vector addresses and priority
FUNCTIONAL DESCRIPTION



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