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M38C31M7AXXXFS 数据表(PDF) 78 Page - Renesas Technology Corp |
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M38C31M7AXXXFS 数据表(HTML) 78 Page - Renesas Technology Corp |
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78 / 224 page ![]() 38C3 Group User’s Manual APPLICATION 2-13 2.2 Timer Fig. 2.2.6 Structure of Timer 34 mode register Fig. 2.2.7 Structure of Timer 56 mode register Timer 34 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M: address 2916) 0: Count operation 1: Count stop b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0: Count operation 1: Count stop 0 0 0: f(XIN)/16 or f(XCIN)/16 0 1: Timer 2 underflow 1 0: f(XIN)/32 or f(XCIN)/32 1 1: f(XIN)/128 or f(XCIN)/128 0 0 0 0: I/O port 1: Timer 3 output 0 0 Timer 3 count stop bit Timer 4 count stop bit Timer 4 count source selection bits Timer 3 output selection bit (P42) Timer 3 count source selection bits Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are “0”. b3 b2 b5 b4 0 0: f(XIN)/16 or f(XCIN)/16 0 1: Timer 3 underflow 1 0: External count input CNTR1 1 1: Not available Timer 56 mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer 56 mode register (T56M: address 2A16) 0: Count operation 1: Count stop b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0: Count operation 1: Count stop 0 0: f(XIN)/16 or f(XCIN)/16 1: Timer 4 underflow 0: Timer mode 1: PWM mode 0 0 0 0: I/O port 1: Timer 6 output 0 0 0 Timer 5 count stop bit Timer 6 count stop bit Timer 6 count source selection bits Timer 6 (PWM) output selection bit (P52) Timer 5 count source selection bit Timer 6 operation mode selection bit Nothing is arranged for this bit. This is a write disabled bit. When this bit is read out, the contents are “0”. b5 b4 0 0: f(XIN)/16 or f(XCIN)/16 0 1: Timer 5 underflow 1 0: Timer 4 underflow 1 1: Not available |
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