M38C31M7AXXXFS datasheet(12/224 Pages) RENESAS

12 / 224 page

38C3 Group User’s Manual

List of figures

Fig. 2.3.8 Serial I/O’s modes ..................................................................................................... 2-38

Fig. 2.3.9 Connection diagram ................................................................................................... 2-38

Fig. 2.3.10 Timing chart .............................................................................................................. 2-39

Fig. 2.3.11 Registers setting relevant to transmission side ................................................... 2-40

Fig. 2.3.12 Registers setting relevant to reception side ......................................................... 2-41

Fig. 2.3.13 Control procedure of transmission side ................................................................ 2-41

Fig. 2.3.14 Control procedure of reception side ...................................................................... 2-42

Fig. 2.3.15 Connection diagram ................................................................................................. 2-43

Fig. 2.3.16 Timing chart .............................................................................................................. 2-43

Fig. 2.3.17 Relevant registers setting ....................................................................................... 2-44

Fig. 2.3.18 Setting of transmission data ................................................................................... 2-44

Fig. 2.3.19 Control procedure ..................................................................................................... 2-45

Fig. 2.3.20 Connection diagram ................................................................................................. 2-46

Fig. 2.3.21 Timing chart .............................................................................................................. 2-47

Fig. 2.3.22 Relevant registers setting in master unit .............................................................. 2-48

Fig. 2.3.23 Relevant registers setting in slave unit ................................................................ 2-48

Fig. 2.3.24 Control procedure of master unit ........................................................................... 2-49

Fig. 2.3.25 Control procedure of slave unit ............................................................................. 2-50

Fig. 2.4.1 Memory map of registers relevant to LCD controller ............................................ 2-52

Fig. 2.4.2 Structure of Segment output enable register ......................................................... 2-53

Fig. 2.4.3 Structure of LCD mode register ............................................................................... 2-53

Fig. 2.4.4 LCD panel ................................................................................................................... 2-54

Fig. 2.4.5 Segment allocation example ..................................................................................... 2-54

Fig. 2.4.6 LCD display RAM map .............................................................................................. 2-55

Fig. 2.4.7 LCD display RAM setting .......................................................................................... 2-55

Fig. 2.4.8 Relevant registers setting ......................................................................................... 2-56

Fig. 2.4.9 Control procedure ....................................................................................................... 2-57

Fig. 2.5.1 Memory map of A-D converter relevant registers ................................................. 2-59

Fig. 2.5.2 Structure of A-D control register .............................................................................. 2-59

Fig. 2.5.3 Structure of A-D conversion register (low-order) ................................................... 2-60

Fig. 2.5.4 Structure of A-D conversion register (high-order) ................................................. 2-60

Fig. 2.5.5 Structure of Interrupt request register 2 ................................................................. 2-61

Fig. 2.5.6 Structure of Interrupt control register 2 .................................................................. 2-61

Fig. 2.5.7 Connection diagram ................................................................................................... 2-62

Fig. 2.5.8 Setting of relevant registers ..................................................................................... 2-62

Fig. 2.5.9 Control procedure ....................................................................................................... 2-63

Fig. 2.6.1 Memory map of ROM correct function relevant registers .................................... 2-65

Fig. 2.6.2 Structure of ROM correct enable register 1 ........................................................... 2-66

Fig. 2.6.3 Connection diagram ................................................................................................... 2-67

Fig. 2.6.4 Setting of relevant registers ..................................................................................... 2-67

Fig. 2.6.5 Control procedure ....................................................................................................... 2-68

Fig. 2.7.1 Example of power-on reset circuit ........................................................................... 2-69

Fig. 2.7.2 RAM backup system example .................................................................................. 2-69

Fig. 2.8.1 Structure of CPU mode register .............................................................................. 2-71

Fig. 2.8.2 Connection diagram ................................................................................................... 2-72

Fig. 2.8.3 Status transition diagram during power failure ...................................................... 2-73

Fig. 2.8.4 Setting of relevant registers ..................................................................................... 2-74

Fig. 2.8.5 Control procedure ....................................................................................................... 2-75

Fig. 2.8.6 Structure of clock counter ......................................................................................... 2-76

Fig. 2.8.7 Initial setting of relevant registers ........................................................................... 2-77

Fig. 2.8.8 Setting of relevant registers after detecting power failure ................................... 2-78

Fig. 2.8.9 Control procedure ....................................................................................................... 2-79

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