M38C31M7AXXXFS datasheet(44/224 Pages) RENESAS

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38C3 Group User’s Manual

HARDWARE

1-29

Fig. 25 Structure of serial I/O control register

Fig. 26 Serial I/O timing (for LSB first)

FUNCTIONAL DESCRIPTION

Serial I/O control register 1

(SIOCON1 : address 001916)

Internal synchronous clock selection bits

b2 b1 b0

0 0 0 : f(XIN)/8 or f(XCIN)/8

0 0 1 : f(XIN)/16 or f(XCIN)/16

0 1 0 : f(XIN)32 or f(XCIN)/32

0 1 1 : f(XIN)/64 or f(XCIN)/64

1 1 0 : f(XIN)/128 or f(XCIN)/128

1 1 1 : f(XIN)/256 or f(XCIN)/256

Serial I/O port selection bit (P40, P45, P46)

0 : I/O port

1 : SOUT, SCLK1, SCLK2 signal pin

SRDY output selection bit (P47)

0 : I/O port

1 : SRDY signal pin

Transfer direction selection bit

0 : LSB first

1 : MSB first

Synchronous clock selection bit

0 : External clock

1 : Internal clock

P-channel output disable bit (P40, P45, P46)

0 : CMOS output (in output mode)

1 : N-channel open-drain (in output mode)

Serial I/O control register 2

(SIOCON2: address 001A16)

Synchronous clock output pin selection bit

0 : SCLK1

1 : SCLK2

Not used (returns “0” when read)

Interrupt request bit set

Synchronous clock

Transfer clock

Serial I/O register

write signal

Serial I/O output

SOUT

Serial I/O input

SIN

Receive enable signal

SRDY

Note: When internal clock is selected, the SOUT pin goes to high impedance after

transfer ends.

(Note)

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