ADATE305 datasheet(39/56 Pages) AD

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ADATE305

Rev. 0 | Page 39 of 56

The ADDR[4:0] bits determine the destination register of the data being written to the ADATE305.

Table 20. Register Selection

DATA[15:0]

CH[1:0]

R/W

ADDR[4:0]

Reset State

N/A1

N/A

0x00

NOP

N/A

DATA[13:0]

CH[1:0]

R/W

0x01

VH DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x02

VL DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x03

VT/VCOM DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x04

VOL DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x05

VOH DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x06

VCH DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x07

VCL DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x08

V(IOH ) DAC level

4096d

DATA[13:0]

CH[1:0]

R/W

0x09

V(IOL ) DAC level

4096d

DATA[13:0]

CH[1]

R/W

0x0A

OVD high level

4096d

DATA[13:0]

CH[0]

R/W

0x0A

OVD low level

4096d

DATA[15:0]

CH[1:0]

R/W

0x0B

PMUDAC level

16384d

DATA[2:0]

CH[1:0]

R/W

0x0C

PE/PMU enable

000b

DATA[2:0]

CH[1:0]

R/W

0x0D

Channel state

000b

DATA[9:0]

CH[1:0]

R/W

0x0E

PMU state

DATA[2:0]

CH[1:0]

R/W

0x0F

PMU measure enable

000b

DATA[0]

CH[1:0]

R/W

0x10

Differential comparator enable

DATA[1:0]

CH[1:0]

R/W

0x11

16-bit DAC monitor

00b

DATA[1:0]

CH[1:0]

R/W

0x12

OVD_CHx alarm mask

01b

DATA[2:0]

CH[1:0]

0x13

OVD_CHx alarm state

N/A

0x14 to 0x1F

Reserved

N/A

1 N/A means not applicable.

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