ADATE305 datasheet(52/56 Pages) AD

部件名	ADATE305

功能描述	250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

PDF	56 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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52 / 56 page

ADATE305

Rev. 0 | Page 52 of 56

PMU

V/I CLAMP

FLAG

–2.5V

OVD LOW LEVEL

DAC (ADDR[4:0] = 0x0A, CH[0])

(ADDR[4:0] = 0x12) DATA[1]

PMU MASK ENABLES PMU V/I

FLAG TO ALARM OVD_CHx PIN

ADATE305

(ADDR[4:0] = 0x12) DATA[0]

OVD MASK ENABLES OVD

FLAGS TO ALARM OVD_CHx PIN

OVD_CHx

SHORT-CIRCUIT

CURRENT = 100µA

(ADDR[4:0] = 0x13) 2 DATA[2] DATA[1] DATA[0]

1THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE

LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED

HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)

2THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.

6.5V

OVD HIGH LEVEL

DAC (ADDR[4:0] = 0x0A, CH[1])

DUT

Figure 84. OVD Block Diagram

ADATE305 数据表(PDF) 52 Page - Analog Devices