ADE5166 datasheet(106/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 106 of 148

TIMERS

Each ADE5166/ADE5169 has three 16-bit timers/counters:

Timer/Counter 0, Timer/Counter 1, and Timer/Counter 2. The

timer/counter hardware is included on-chip to relieve the processor

core of overhead inherent in implementing timer/counter func-

tionality in software. Each timer/counter consists of two 8-bit

registers: THx and TLx (x = 0, 1, or 2). All three timers can be

configured to operate as timers or as event counters.

When functioning as a timer, the TLx SFR is incremented every

machine cycle. Thus, it can be thought of as counting machine

cycles. Because a machine cycle on a single cycle core consists of

one core clock period, the maximum count rate is the core clock

frequency.

When functioning as a counter, the TLx register is incremented

by a 1-to-0 transition at its corresponding external input pin:

T0, T1, or T2. When the samples show a high in one cycle and a

low in the next cycle, the count is incremented. Because it takes

two machine cycles (two core clock periods) to recognize a 1-to-0

transition, the maximum count rate is half the core clock frequency.

There are no restrictions on the duty cycle of the external input

signal, but to ensure that a given level is sampled at least once

before it changes, it must be held for a minimum of one full

machine cycle. User configuration and control of all timer

operating modes is achieved via the SFRs listed in Table 111.

Table 111. Timer SFRs

SFR

Address

Bit Addressable

Description

TCON

0x88

Yes

Timer/Counter 0 and Timer/Counter 1 control (see Table 113).

TMOD

0x89

Timer/Counter 0 and Timer/Counter 1 mode (see Table 112).

TL0

0x8A

Timer 0 low byte (see Table 116).

TL1

0x8B

Timer 1 low byte (see Table 118).

TH0

0x8C

Timer 0 high byte (see Table 115).

TH1

0x8D

Timer 1 high byte (see Table 117).

T2CON

0xC8

Yes

Timer/Counter 2 control (see Table 114).

RCAP2L

0xCA

Timer 2 reload/capture low byte (see Table 122).

RCAP2H

0xCB

Timer 2 reload/capture high byte (see Table 121).

TL2

0xCC

Timer 2 low byte (see Table 120).

TH2

0xCD

Timer 2 high byte (see Table 119).

TIMER REGISTERS

Table 112. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, Address 0x89)

Bit

Mnemonic

Default

Description

Gate1

Timer 1 gating control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and the TR1

control bit (Address 0x88[6]) is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set.

C/T1

Timer 1 timer or counter select bit. Set by software to select counter operation (input from T1 pin). Cleared

by software to select the timer operation (input from internal system clock).

[5:4]

T1/M1,

T1/M0

Timer 1 mode select bits.

T1/M1, T1/M0

Result

TH1 (Address 0x8D) operates as an 8-bit timer/counter. TL1 (Address 0x8B) serves as a

5-bit prescaler.

16-bit timer/counter. TH1 and TL1 are cascaded; there is no prescaler.

8-bit autoreload timer/counter. TH1 holds a value to reload into TL1 each time it overflows.

Timer/Counter 1 stopped.

Gate0

Timer 0 gating control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the TR0

control bit (Address 0x88[4]) is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set

in the Timer/Counter 0 and Timer/Counter 1 control SFR (TCON, Address 0x88).

C/T0

Timer 0 timer or counter select bit. Set by software to the select counter operation (input from the T0 pin).

Cleared by software to the select timer operation (input from internal system clock).

[1:0]

T0/M1,

T0/M0

Timer 0 mode select bits.

T0/M1, T0/M0

Result

TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.

16-bit timer/counter. TH0 and TL0 are cascaded; there is no prescaler.

8-bit autoreload timer/counter. TH0 holds a value to reload into TL0 each time TL0 overflows.

TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an

8-bit timer only, controlled by Timer 1 control bits.

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