MPC5633MMLL80 datasheet(26/106 Pages) FREESCALE

26 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

•

Channels 1, 3, 5 and 6 support modes:

— General Purpose Input/Output (GPIO)

— Single Action Input Capture (SAIC)

— Single Action Output Compare (SAOC)

•

Channels 2, 4, 11 and 13 support all the modes above plus:

— Output Pulse Width Modulation Buffered (OPWMB)

•

Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:

— Input Period Measurement (IPM)

— Input Pulse Width Measurement (IPWM)

— Double Action Output Compare (set flag on both matches) (DAOC)

— Modulus Counter Buffered (MCB)

— Output Pulse Width and Frequency Modulation Buffered (OPWFMB)

•

Three 24-bit wide counter buses

— Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can use it as a reference

— Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference

— Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a reference

•

Shared time bases with the eTPU through the counter buses

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Synchronization among internal and external time bases

2.3.13

eTPU2

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes

instructions and real-time input events, performs output waveform generation, and accesses shared data without host

intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful

timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler

and documentation allows customers to develop their own functions on the eTPU2.

The eTPU2 includes these distinctive features:

•

The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input

[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.

•

Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this

enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.

•

A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture

characteristics of this channel mode can be programmed via microcode.

•

Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can

also be requested simultaneously at the same instruction.

•

Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.

•

Channel digital filters can be bypassed.

•

The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input

[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.

•

Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this

enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.

•

A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture

characteristics of this channel mode can be programmed via microcode.

•

Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can

also be requested simultaneously at the same instruction.

•

Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.

•

Channel digital filters can be bypassed.

MPC5633MMLL80 数据表(PDF) 26 Page - Freescale Semiconductor, Inc

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