MPC5633MMLL80 datasheet(35/106 Pages) FREESCALE

35 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

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Host processor (e200) development support features

— IEEE-ISTO 5001-2003 standard class 2 compliant

— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities

(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires

between the discontinuities. Thus, static code may be traced.

— Watchpoint trigger enable of program trace messaging

— Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be halted when the CPU writes a

specific value to a memory location

– 4 data value breakpoints

–CPU only

– Detects ‘equal’ and ‘not equal’

– Byte, half word, word (naturally aligned)

NOTE

This feature is imprecise due to CPU pipelining.

— Subset of Power Architecture software debug facilities with OnCE block (Nexus class 1 features)

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eTPU development support features

— IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU

— Nexus based breakpoint configuration and single step support (JTAG feature of the eTPU)

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Run-time access to the on-chip memory map via the Nexus read/write access protocol. This feature supports accesses

for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid

prototyping for powertrain automotive development systems.

•

All features are independently configurable and controllable via the IEEE 1149.1 I/O port

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Power-on-reset status indication during reset via MDO[0] in disabled and reset modes

2.3.20.2

JTAG

The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent

to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001

standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant

with the IEEE 1149.1-2001 standard and supports the following features:

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IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)

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A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP

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A 5-bit instruction register that supports the additional following public instructions:

— ACCESS_AUX_TAP_NPC

— ACCESS_AUX_TAP_ONCE

— ACCESS_AUX_TAP_eTPU

— ACCESS_CENSOR

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3 test data registers to support JTAG Boundary Scan mode

— Bypass register

— Boundary scan register

— Device identification register

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A TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

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Censorship Inhibit Register

— 64-bit Censorship password register

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