 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
MPC5633MMLL80 数据表(PDF) 98 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC5633MMLL80 数据表(HTML) 98 Page - Freescale Semiconductor, Inc |
|
|
98 / 106 page  MPC5634M Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 98 Figure 8. Pad output delay 4.16 AC timing 4.16.1 IEEE 1149.1 interface timing Table 33. JTAG pin AC electrical characteristics1 # Symbol C Characteristic Min. Value Max. Value Unit 1tJCYC CC D TCK Cycle Time 100 — ns 2tJDC CC D TCK Clock Pulse Width 40 60 ns 3tTCKRISE CC D TCK Rise and Fall Times (40% – 70%) — 3 ns 4tTMSS, tTDIS CC D TMS, TDI Data Setup Time 5 — ns 5tTMSH, tTDIH CC D TMS, TDI Data Hold Time 25 — ns 6tTDOV CC D TCK Low to TDO Data Valid — 23 ns 7tTDOI CC D TCK Low to TDO Data Invalid 0 — ns 8tTDOHZ CC D TCK Low to TDO High Impedance — 20 ns 9tJCMPPW CC D JCOMP Assertion Time 100 — ns 10 tJCMPS CC D JCOMP Setup Time to TCK Low 40 — ns 11 tBSDV CC D TCK Falling Edge to Output Valid — 50 ns VDDE/2 VOH VOL Rising Edge Output Delay Falling Edge Output Delay Pad Data Input Pad Output |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
