MPC5633MMLL80 datasheet(58/106 Pages) FREESCALE

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19 ALT_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI/Up otherwise.

20 In 176-pin and 208-pin packages, the Nexus function is disabled and the pin/ball has the secondary function

21 This signal is not available in the 176-pin and 208-pin packages.

22 The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.

23 TDI and TDO are required for JTAG operation.

24 The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.

25 The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.

26 ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.

27 eTPU_A[25] is an output only function.

28 Only the output channels of eTPU[8:9] are connected to pins.

29 Only the output of eMIOS[12] is connected to the pin. The DSPI_C_SOUT is not available in this device.

30 The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function

and should be grounded.

31 The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the

valid operating voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.

32 VSSPLL and VSSREG are connected to the same pin.

33 This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv.

34 This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv.

35 VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy

naming, however they should be considered as the same signal in this document.

36 LVDS pins will not work at 3.3 V.

37 The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for

analog input function.

38 VDDEH6A and VDDEH6B are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however

they should be considered as the same signal in this document.

39 If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived

from the 5 volt power supply.

40 In the calibration package this signal is named VDDE12.

MPC5633MMLL80 数据表(PDF) 58 Page - Freescale Semiconductor, Inc

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