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ADE7858ACPZ 数据表(PDF) 62 Page - Analog Devices

部件名 ADE7858ACPZ
功能描述  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7858ACPZ 数据表(HTML) 62 Page - Analog Devices

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ADE7858
Preliminary Technical Data
Rev. PrA| Page 62 of 76
Address
Name
R/W1
Bit
Length
Bit Length
during
comm2
Type3
Default
Value
Description
0xE610
CFMODE
R/W
16
16
U
0x0E88
CFx, x=1,2,3 configuration register. (See Table 36)
0xE611
CF1DEN
R/W
16
16
U
0x0000
CF1 denominator
0xE612
CF2DEN
R/W
16
16
U
0x0000
CF2 denominator
0xE613
CF3DEN
R/W
16
16
U
0x0000
CF3 denominator
0xE614
APHCAL
R/W
10
16 ZP
U
0x0000
Phase calibration of phase A. (See Table 37)
0xE615
BPHCAL
R/W
10
16 ZP
U
0x0000
Phase calibration of phase B. (See Table 37)
0xE616
CPHCAL
R/W
10
16 ZP
U
0x0000
Phase calibration of phase C. (See Table 37)
0xE617
PHSIGN
R
16
16
U
NA
Power sign register. (See Table 38)
0xE618
CONFIG
R/W
16
16
U
0x0000
ADE7858 configuration register. (See Table 39)
0xE700
MMODE
R/W
8
8
U
0x16
Measurement mode register. (See Table 40)
0xE701
ACCMODE
R/W
8
8
U
0x00
Accumulation mode register. (SeeTable 41)
0xE702
LCYCMODE
R/W
8
8
U
0x78
Line accumulation mode behavior. (See Table 42)
0xE703
PEAKCYC
R/W
8
8
U
0x00
Peak detection half line cycles
0xE704
SAGCYC
R/W
8
8
U
0x00
Sag detection half line cycles
0xE705
CFCYC
R/W
8
8
U
0x01
Number of CF pulses between two consecutive
energy latches. See Synchronizing energy registers
with CFx outputs section
0xE706
HSDC_CFG
R/W
8
8
U
0x00
HSDC configuration register. (See Table 43)
0xE707
VERSION
R/W
8
8
U
-
Version of die
0xEBFF
reserved
8
8
This address may be used in manipulating the
SS pin when SPI is chosen as the active port. (See
Serial Interfaces chapter for details)
0xEC00
Reserved
N/A
N/A
N/A
N/A
N/A
For proper operation, do not write to this address.
0xEC01
CONFIG2
R/W
8
8
U
0x00
Configuration register used during PSM1 mode. (See
Table 44)
1 R=read
W=write
2 32 ZP=24 or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or respectively 12 most significant bits padded with 0s
32 SE=24-bit signed register that is transmitted as a 32-bit word sign extended to 32 bits
16 ZP=10-bit unsigned register that is transmitted as a 16-bit word with 6 most significant bits padded with 0s
3 U=unsigned register
S=signed register in two’s complement format



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