ADE7858ACPZ datasheet(23/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 23 of 76

similar processing chains. The ADC outputs are signed twos

complement 24-bit words and are available at a rate of 8 kSPS.

With the specified full-scale analog input signal of ±0.5 V, the

ADC produces its maximum output code value. This diagram

shows a full-scale voltage signal being applied to the differential

inputs VA and VN. The ADC output swings between

−5,928,256 (0xA558AC0) and +5,928,256 (0x5A7540).

Voltage Waveform Gain Registers

There is a multiplier in the signal path of each phase voltage.

The voltage waveform can be changed by ±100% by writing a

correspondent twos complement number to the 24-bit signed

current waveform gain registers (AVGAIN[23:0],

BVGAIN[23:0] and CVGAIN[23:0]). For example, if 0x400000

is written to those registers, the ADC output is scaled up by

50%. To scale the input by -50%, write 0xC00000 to the

registers. Equation (4) describes mathematically the function of

the current waveform gain registers.

















Gain

Voltage

Content

Output

waveform

Voltage

(4)

Changing the content of AVGAIN[23:0], BVGAIN[23:0] and

CVGAIN[23:0] affects all calculations based on its voltage; that

is, it affects the corresponding phase active/reactive/apparent

energy and voltage rms calculation. In addition, waveform

samples are also scaled accordingly.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words and the DSP works on 28 bits. As

presented in Figure 15, AVGAIN, BVGAIN and CVGAIN

registers are accessed as 32-bit registers with 4 most significant

bits padded with 0s and sign extended to 28 bits.

Voltage Channel HPF

As seen in Current Channel HPF section, the ADC outputs can

contain a dc offset that can create errors in power and rms

calculations. High Pass Filters (HPF) are placed in the signal

path of the phase voltages, similar to the ones in the current

channels. HPFDIS[23:0] register may enable or disable the

filters. See Current Channel HPF section for more details.

Voltage Channel Sampling

The waveform samples of the current channel are taken at the

output of HPF and stored into VAWV, VBWV and VCWV 24-

bit signed registers at a rate of 8kSPS. All power and rms

calculations remain uninterrupted during this process. Bit 17

(DREADY) in STATUS0[31:0] register is set when VAWV,

VBWV and VCWV registers are available to be read using I2C

or SPI serial ports. Setting bit 17 (DREADY) in MASK0[31:0]

set. See Digital Signal Processor chapter for more details on bit

DREADY.

VAP

PGA3

ADC

PGA3 bits

GAIN[8:6]

x1, x2, x4,x8,

x16

REFERENCE

HPF

VOLTAGE RMS (VRMS)

CALCULATION

VAWV WAVEFORM

SAMPLE REGISTER

TOTAL ACTIVE POWER

CALCULATION

+0.5V/GAIN

-0.5V/GAIN

ANALOG INPUT RANGE

ADC OUTPUT RANGE

VOLTAGE CHANNEL

DATA RANGE

ZX SIGNAL

DATA RANGE

DSP

LPF1

ZX DETECTION

VOLTAGE PEAK,

OVERVOLTAGE, SAG

DETECT

0x5A7540=

5,928,256

0xA58AC0=

-5,928,256

0x5A7540=

5,928,256

0xA58AC0=

-5,928,256

AVGAIN[23:0]

HPFDIS[23:0]

Figure 22. Voltage Channel Data Path

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words. Similar to registers presented in Figure 18,

VAWV, VBWV and VCWV 24-bit signed registers are

transmitted signed extended to 32 bits.

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