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ADE7858ACPZ 数据表(PDF) 9 Page - Analog Devices |
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ADE7858ACPZ 数据表(HTML) 9 Page - Analog Devices |
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9 / 76 page  Preliminary Technical Data ADE7858 Rev. PrA | Page 9 of 76 Table 4. HSDC INTERFACE TIMING Parameter Parameter Symbol Min Max Unit HSA to SCLK edge tSS 0 ns HSCLK period 125 HSCLK low pulse width tSL 50 ns HSCLK high pulse width tSH 50 ns Data output valid after HSCLK edge tDAV 5 40 ns Data output fall time tDF 20 ns Data output rise time tDR 20 ns HSCLK rise time tSR 10 ns HSCLK fall time tSF 10 ns HSD disable after HAS rising edge tDIS 40 ns HSA high after HSCLK edge tSFS 0 ns HSCLK HSD t SS t SL t SH t DF t DR t SR t SF t SFS t DIS MSB INTERMEDIATE BITS LSB t DAV HSA Figure 4. HSDC Interface Timing Figure 5. Load Circuit for Timing Specifications 200µA IOL 1.6mA IOH 2.1V TO OUTPUT PIN CL 50pF |
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